Specified target 0.15mm process for silkscreen.

This commit is contained in:
CarlPoirier 2014-07-01 20:07:56 -04:00
parent 774dc13a62
commit a721bc498e

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@ -60,7 +60,7 @@ TODO
6.2. Pad 1 is on the left first, then at the top, except at the top for PLCC (IPC-7351).
6.3. For through-hole components, origin is set on pad 1.
6.4. For surface-mount devices, origin is placed in the middle with respect to device lead ends (IPC-7351).
6.5. Silkscreen is not superposed to pads, is completely visible after board assembly, and provides a reference mark for pin 1.
6.5. Silkscreen is not superposed to pads, is completely visible after board assembly, uses 0.15mm line width and provides a reference mark for pin 1. (IPC-7351)
6.6. Cannot be duplicated to match a different pin ordering. This is to be handled in the symbol libraries.