44 lines
756 B
Prolog
44 lines
756 B
Prolog
|
update=Mo 21 Jan 2019 20:16:43 CET
|
||
|
version=1
|
||
|
last_client=kicad
|
||
|
[general]
|
||
|
version=1
|
||
|
RootSch=
|
||
|
BoardNm=
|
||
|
[cvpcb]
|
||
|
version=1
|
||
|
NetIExt=net
|
||
|
[eeschema]
|
||
|
version=1
|
||
|
LibDir=
|
||
|
[eeschema/libraries]
|
||
|
[pcbnew]
|
||
|
version=1
|
||
|
PageLayoutDescrFile=
|
||
|
LastNetListRead=receive_v1_1.net
|
||
|
PadDrill=0.762
|
||
|
PadDrillOvalY=0.762
|
||
|
PadSizeH=1.524
|
||
|
PadSizeV=1.524
|
||
|
PcbTextSizeV=1.5
|
||
|
PcbTextSizeH=1.5
|
||
|
PcbTextThickness=0.3
|
||
|
ModuleTextSizeV=1
|
||
|
ModuleTextSizeH=1
|
||
|
ModuleTextSizeThickness=0.15
|
||
|
SolderMaskClearance=0.2
|
||
|
SolderMaskMinWidth=0
|
||
|
DrawSegmentWidth=0.2
|
||
|
BoardOutlineThickness=0.15
|
||
|
ModuleOutlineThickness=0.15
|
||
|
[schematic_editor]
|
||
|
version=1
|
||
|
PageLayoutDescrFile=empty.kicad_wks
|
||
|
PlotDirectoryName=
|
||
|
SubpartIdSeparator=0
|
||
|
SubpartFirstId=65
|
||
|
NetFmtName=
|
||
|
SpiceAjustPassiveValues=0
|
||
|
LabSize=50
|
||
|
ERC_TestSimilarLabels=1
|