811 lines
12 KiB
Plaintext
811 lines
12 KiB
Plaintext
EESchema-DOCLIB Version 2.0 Date: 08/11/2011 08:57:41
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#
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$CMP 7400
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D Quad nand2
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K TTL nand2
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$ENDCMP
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#
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$CMP 7402
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D Quad Nor2
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K TTL Nor2
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$ENDCMP
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#
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$CMP 74HC00
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D Quad nand2
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K HCMOS nand2
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$ENDCMP
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#
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$CMP 74HC02
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D Quad Nor2
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K HCMOS Nor2
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$ENDCMP
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#
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$CMP 74HC04
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D Hex Inverseur
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K HCMOS not inv
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$ENDCMP
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#
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$CMP 74HC245
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D Octal BUS Transceivers, 3 State out
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K HCMOS BUS 3State
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$ENDCMP
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#
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$CMP 74HC595
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D 8 bits serial in // out Shift Register 3 State Out
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K HCMOS SR 3State
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F 74xx/74HC595.pdf
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$ENDCMP
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#
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$CMP 74HC74
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D Dual D FlipFlop, Set & Reset
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K TTL DFF
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F 74xx/74hc_hct74.pdf
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$ENDCMP
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#
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$CMP 74HCT00
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D Quad nand2
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K HCTMOS nand2
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$ENDCMP
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#
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$CMP 74HCT02
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D Quad Nor2
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K HCTMOS Nor2
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$ENDCMP
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#
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$CMP 74HCT04
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D Hex Inverseur
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K HCTMOS not inv
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$ENDCMP
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#
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$CMP 74HCT541_PWR
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D 8bits Buffer/Line Driver 3 state Out
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K TTL BUFFER 3State BUS
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$ENDCMP
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#
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$CMP 74HCT574_PWR
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D 8 bits Register, 3 state Out, with visible Pins power
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K TTL REG DFF DFF8 3State
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$ENDCMP
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#
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$CMP 74LS00
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D Quad nand2
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K TTL nand2
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$ENDCMP
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#
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$CMP 74LS01
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D Quad nand2 open collect.
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K TTL nand2 opencol
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$ENDCMP
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#
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$CMP 74LS02
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D Quad Nor2
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K TTL Nor2
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$ENDCMP
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#
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$CMP 74LS03
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D Quad Nand2 open collect
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K TTL Nand2 OpenCol
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$ENDCMP
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#
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$CMP 74LS04
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D Hex Inverseur
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K TTL not inv
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$ENDCMP
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#
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$CMP 74LS05
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D Inverseur Open Collect
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K TTL not inv OpenCol
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$ENDCMP
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#
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$CMP 74LS08
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D Quad And2
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K TTL and2
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$ENDCMP
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#
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$CMP 74LS09
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D Quad And2 Open Collect
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K TTL and2 OpenCol
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$ENDCMP
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#
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$CMP 74LS10
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D Triple Nand3
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K TTL Nand3
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$ENDCMP
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#
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$CMP 74LS107
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D Double JK FlipFlop, reset
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K TTL JK
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$ENDCMP
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#
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$CMP 74LS109
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D Double JK FlipFlop, Set & Reset
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K TTL JK
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$ENDCMP
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#
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$CMP 74LS11
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D Triple And3
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K TTL And3
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$ENDCMP
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#
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$CMP 74LS112
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D Double JK FlipFlop, Set & Reset
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K TTL JK
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$ENDCMP
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#
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$CMP 74LS113
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D Double JK, Set
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K TTL JK
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$ENDCMP
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#
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$CMP 74LS114
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D Double JK, common Clock & Reset, Set
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K TTL JK
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$ENDCMP
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#
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$CMP 74LS12
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D Triple Nand3 Open Collect
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K TTL Nand3 OpenCol
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$ENDCMP
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#
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$CMP 74LS122
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D Retriggerable Monostable
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K TTL monostable
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$ENDCMP
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#
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$CMP 74LS123
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D Dual retriggerable Monostable
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K TTL monostable
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$ENDCMP
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#
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$CMP 74LS125
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D Quad buffer 3 State out
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K TTL buffer 3State
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$ENDCMP
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#
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$CMP 74LS126
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D Quad buffer 3 State out
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K TTL Buffer 3State
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$ENDCMP
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#
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$CMP 74LS13
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D Double Nand4 schmitt trigger
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K TTL Nand4
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$ENDCMP
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#
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$CMP 74LS132
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D Quad Nand2 schmitt trigger
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K TTL Nand2
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$ENDCMP
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#
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$CMP 74LS133
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D Nand 8 inputs
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K TTL Nand8
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$ENDCMP
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#
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$CMP 74LS136
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D Quad Exclusive Or 2-inputs, Open Collect.
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K TTL XOR2 OpenCol
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$ENDCMP
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#
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$CMP 74LS137
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D Decoder 3 to 8, addr latches.
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K TTL DECOD8 DECOD
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$ENDCMP
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#
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$CMP 74LS138
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D Decoder 3 to 8 (active low outputs)
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K TTL DECOD DECOD8
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$ENDCMP
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#
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$CMP 74LS139
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D Dual Decoder 1 of 4, Active low outputs
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K TTL DECOD4
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$ENDCMP
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#
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$CMP 74LS14
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D Hex inverseur schmitt trigger
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K TTL not inv
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$ENDCMP
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#
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$CMP 74LS145
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D Decoder 1 to 10, Open Collect.
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K TTL DECOD10 OpenColl
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$ENDCMP
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#
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$CMP 74LS147
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D Priority Encodeur, 10 to 4
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K TTL ENCOD
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$ENDCMP
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#
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$CMP 74LS148
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D Priority Encoder 3 to 8 cascadable
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K TTL ENCOD
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$ENDCMP
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#
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$CMP 74LS15
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D Triple And 3 inputs
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K TTL And3
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$ENDCMP
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#
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$CMP 74LS151
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D Multiplexer 8 to 1
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K TTL MUX8
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$ENDCMP
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#
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$CMP 74LS153
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D Dual Multiplexer 4 to 1
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K TTL Mux4
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$ENDCMP
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#
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$CMP 74LS154
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D Decoder 4 to 16
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K TTL DECOD16 DECOD
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$ENDCMP
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#
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$CMP 74LS155
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D Dual 2 to 4 lines Decoder/Demultiplexer
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K TTL DECOD8 DECOD4 DEMUX4 DEMUX8 DEMUX DECOD
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$ENDCMP
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#
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$CMP 74LS156
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D Dual 2 to 4 lines Decoder/Demultiplexer, Open Collect.
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K TTL DECOD8 DECOD4 DEMUX4 DEMUX8 OpenCol
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$ENDCMP
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#
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$CMP 74LS157
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D Quad 2 to 1 line Multiplexer
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K TTL MUX MUX2
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$ENDCMP
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#
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$CMP 74LS158
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D Quad 2 to 1 multiplexer
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K TTL Mux MUX2
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$ENDCMP
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#
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$CMP 74LS160
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D Sychronous 4 bits programmable decimal Counter
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K TTL CNT CNT4
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$ENDCMP
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#
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$CMP 74LS161
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D Sychronous 4 bits programmable binary Counter
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K TTL CNT CNT4
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$ENDCMP
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#
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$CMP 74LS162
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D Sychronous 4 bits programmable decimal Counter
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K TTL CNT CNT4
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$ENDCMP
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#
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$CMP 74LS163
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D Sychronous 4 bits programmable binary Counter
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K TTL CNT CNT4
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$ENDCMP
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#
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$CMP 74LS165
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D Shift Register 8 bits, parallel load
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K TTL SR SR8
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$ENDCMP
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#
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$CMP 74LS166
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D Shift Register 8 bits, parallel load
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K TTL SR SR8
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$ENDCMP
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#
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$CMP 74LS168
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D Synchronous 4 bits Up/Down Decimal counter
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K TTL CNT CNT4
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$ENDCMP
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#
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$CMP 74LS169
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D Synchronous 4 bits Up/Down binary counter
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K TTL CNT CNT4
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$ENDCMP
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#
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$CMP 74LS170
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D 4 x 4 Register Files Open Collect.
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K TTL Register OpenCol
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$ENDCMP
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#
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$CMP 74LS173
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D 4 bits D-type Register, 3 state out
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K TTL REG REG4 3State DFF
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$ENDCMP
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#
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$CMP 74LS174
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D Hex D-type FlipFlop, reset
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K TTL REG REG6 DFF
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$ENDCMP
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#
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$CMP 74LS175
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D 4 bits D FlipFlop, reset
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K TTL REG REG4 DFF
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$ENDCMP
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#
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$CMP 74LS181
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D Arithmetic logic unit
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K TTL ALU ARITH
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F 74xx/74F181.pdf
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$ENDCMP
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#
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$CMP 74LS182
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D Carry generator
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K TTL ALU ARITH
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$ENDCMP
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#
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$CMP 74LS190
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D 4 bits Synchronous 4 bits Up/Down BCD Counter
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K TTL CNT CNT4
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$ENDCMP
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#
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$CMP 74LS191
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D 4 bits Synchronous 4 bits Up/Down binary Counter
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K TTL CNT CNT4
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$ENDCMP
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#
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$CMP 74LS192
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D Synchronous 4 bits Up/Down (2 clk) counter
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K TTL CNT CNT4
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$ENDCMP
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#
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$CMP 74LS193
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D Synchronous 4 bits Up/Down (2 clk) counter
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K TTL CNT CNT4
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$ENDCMP
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#
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$CMP 74LS194
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D Shift Register 4 bits Bidirectionnel
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K TTL RS SR4
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$ENDCMP
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#
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$CMP 74LS195
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D Shift Register 4 bits, parallel
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K TTL SR SR4
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$ENDCMP
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#
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$CMP 74LS196
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D 4 (3 + 1 ) bits presettable BCD counter
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K TTL CNT CNT4
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$ENDCMP
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#
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$CMP 74LS197
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D 4 (3 + 1 ) bits presettable binary counter
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K TTL CNT CNT4
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$ENDCMP
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#
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$CMP 74LS20
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D Dual Nand 4 inputs
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K TTL Nand4
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$ENDCMP
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#
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$CMP 74LS21
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D Dual And 4 inputs
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K TTL And4
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$ENDCMP
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#
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$CMP 74LS22
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D Dual Nand 4 inputs Open Collect.
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K TTL Nand4 OpenCol
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$ENDCMP
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#
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$CMP 74LS221
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D Dual Monostable
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K TTL Monostable
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$ENDCMP
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#
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$CMP 74LS240
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D 8 bits BUS Buffer (Inverter) 3 State out
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K TTL Buffer BUS 3State
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$ENDCMP
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#
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$CMP 74LS241
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D 8 bits Bus Buffer 3 State out
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K TTL Buffer BUS 3State
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$ENDCMP
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#
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$CMP 74LS243
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D 4 bits Bus Tranceiver
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K TTL Buffer 3State BUS BIDI
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$ENDCMP
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#
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$CMP 74LS244
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D 8 bits Bus Buffer 3 State out
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K TTL Buffer BUS 3State
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$ENDCMP
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#
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$CMP 74LS245
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D Octal BUS Transceivers, 3 State out
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K TTL BUS 3State
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$ENDCMP
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#
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$CMP 74LS246
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D BDC to 7 segments Decoder Open Collec. active Low
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K TTL DECOD
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$ENDCMP
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#
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$CMP 74LS247
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D BDC to 7 segments Decoder Open Collec. active Low
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K TTL DECOD
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$ENDCMP
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#
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$CMP 74LS248
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D BCD to 7 segments Decoder, Active High
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K TTL DECOD
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$ENDCMP
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#
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$CMP 74LS249
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D BCD to 7 segments Decoder, Open collect, Active High
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K TTL DECOD OpenCol
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$ENDCMP
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#
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$CMP 74LS251
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D Multiplexer 8 to 1, 3 state Out
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K TTL MUX MUX8 3State
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$ENDCMP
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#
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$CMP 74LS253
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D Dual Multiplexer 4 to 1, 3 State Out
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K TTL MUX MUX4 3State
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$ENDCMP
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#
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$CMP 74LS257
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D Quad 2 to 1 Multiplexer
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K TTL MUX MUX2
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$ENDCMP
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#
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$CMP 74LS258
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D Quad 2 to 1 Multiplexer,invert
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K TTL MUX MUX2
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$ENDCMP
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#
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$CMP 74LS259
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D 8 bits addressable latch
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K TTL REG DFF
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$ENDCMP
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#
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$CMP 74LS26
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D Quad Nand 2 inputs Open collect.
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K TTL Nand2 OpenCol
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$ENDCMP
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#
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$CMP 74LS27
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D Triple Nr 3 inputs
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K TTL Nor3
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$ENDCMP
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#
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$CMP 74LS273
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D 8 bits D FlipFlop, reset
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K TTL DFF DFF8
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$ENDCMP
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#
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$CMP 74LS28
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D Quad Buffer Nor2
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K TTL Nor2 Buffer
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$ENDCMP
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#
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$CMP 74LS280
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D Parity Generator/Checker
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K TTL ALU Arith
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$ENDCMP
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#
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$CMP 74LS283
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D 4 bits full Adder
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K TTL ADD Arith ALU
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$ENDCMP
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#
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$CMP 74LS290
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D 4 bits BCD counter
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K TTL CNT CNT4
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$ENDCMP
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#
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$CMP 74LS293
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D 4 bits binary counter
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K TTL CNT CNT4
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$ENDCMP
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#
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$CMP 74LS298
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D Quad 2 to 1 multiplexer with storage
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K TTL MUX MUX2
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$ENDCMP
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#
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$CMP 74LS299
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D 8 bits Universer shift/storage Register
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K TTL REG SR SR8
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$ENDCMP
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#
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$CMP 74LS30
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D Nand 8 inputs
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K TTL Nand8
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$ENDCMP
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#
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$CMP 74LS32
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D Quad Or 2 inputs
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K TTL Or2
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$ENDCMP
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#
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$CMP 74LS323
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D 8 bits Universal Shift/Storage Register
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K TTL REG SR SR8
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$ENDCMP
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#
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$CMP 74LS33
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D Quad Nand 2 inputs, Open collect.
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K TTL Nand8 OpenCol
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$ENDCMP
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#
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$CMP 74LS348
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D 8 to 3 lines Priority Encoder
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K TTL ENCOD Arith
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$ENDCMP
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#
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$CMP 74LS352
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D Dual 4 to 1 line Multiplexer
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K TTL Mux MUX4
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$ENDCMP
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#
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$CMP 74LS353
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D Dual 4 to 1 line Multiplexer, inverter
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K TTL MUX MUX2
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$ENDCMP
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#
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$CMP 74LS365
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D Hex Bus Driver, 3 State Out
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K TTL Buffer BUS 3State
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$ENDCMP
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#
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$CMP 74LS366
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D Hex Bus Driver inverter, 3 state out
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K TTL Buffer BUS 3State
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$ENDCMP
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#
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$CMP 74LS367
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D Hex Bus Driver 3 state Out
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K TTL Buffer BUS 3State
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$ENDCMP
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#
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$CMP 74LS368
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D Hex Bus Driver inverter, 3 state Out
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K TTL Buffer BUS 3State
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$ENDCMP
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#
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$CMP 74LS37
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D Quad Buffer nand2
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K TTL nand2 buffer
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$ENDCMP
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#
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$CMP 74LS373
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D 8 bits Latch, 3 state Out
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K TTL REG DFF DFF8 LATCH
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$ENDCMP
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#
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$CMP 74LS374
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D 8 bits Register, 3 state Out
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K TTL DFF DFF8 REG 3State
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$ENDCMP
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#
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$CMP 74LS375
|
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D 4 bits Latch
|
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K TTL DFF DFF4 Latch
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$ENDCMP
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#
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$CMP 74LS377
|
|
D 8 bit Register
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K TTL REG DFF DFF8
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$ENDCMP
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#
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$CMP 74LS378
|
|
D 6 bits Register
|
|
K TTL REG DFF DFF6
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$ENDCMP
|
|
#
|
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$CMP 74LS379
|
|
D 4 bits Register
|
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K TTL REG DFF DFF4
|
|
$ENDCMP
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#
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$CMP 74LS38
|
|
D Quad Buffer Nand 2 inputs Open collect.
|
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K TTL Nand2 OpenCol Buffer
|
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$ENDCMP
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|
#
|
|
$CMP 74LS385
|
|
D Quad serial Adder
|
|
K TTL ADD Arith ALU
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS386
|
|
D Quad 2 input XOR
|
|
K TTL XOR2
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS390
|
|
D Dual BDC 4 bits counter
|
|
K TTL CNT CNT4
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS393
|
|
D Dual BDC 4 bits counter
|
|
K TTL CNT CNT4
|
|
F 74xx\74LS393.pdf
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS395
|
|
D 4 bits universal shift register, 3 state out
|
|
K TTL SR SR4 REG 3State
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS398
|
|
D Quad 2 to 1 line Multiplexer, 3 state out
|
|
K TTL MUX MUX2 3State
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS399
|
|
D Quad 2 to 1 line multiplexer with storage
|
|
K TTL MUX MUX2
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS40
|
|
D Dual Nand 4 inputs
|
|
K TTL Nand4
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS42
|
|
D 4 to 10 line DECODER
|
|
K TTL DECOD DECOD10
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS46
|
|
D BCD to 7 segments Driver, Open Collect, 15V outputs
|
|
K TTL DECOD DECOD7 OpenCol
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS47
|
|
D BCD to 7 segments Driver, Open Collect, 30V outputs
|
|
K TTL DECOD DECOD7 OpenCol
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS48
|
|
D BCD to 7 segments Decoder/driver, Active High outputs
|
|
K TTL DECOD DECOD7
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS49
|
|
D BDC to 7 segments decoder/driver, Open collect.
|
|
K TTL DECOD DECOD7 OpenCol
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS51
|
|
D Dual And-Nor ( S =/(AB+CD) )
|
|
K TTL ANDNOR
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS54
|
|
D And-Nor (S = /(AB + CD + EF + GH) )
|
|
K TTL ANDNOR
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS540
|
|
D 8 bits Buffer/Line driver Inverter, 3 state Out
|
|
K BUFFER BUS TTL 3State
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS541
|
|
D 8bits Buffer/Line Driver 3 state Out
|
|
K TTL BUFFER 3State BUS
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS55
|
|
D AND-NOR ( S = / (ABCD + EFGH) )
|
|
K TTL ANDNOR
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS573
|
|
D 8 bits Latch 3 state Out
|
|
K TTL DFF DFF8 LATCH 3State
|
|
F 74xx/74hc573.pdf
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS574
|
|
D 8 bits Register, 3 state Out
|
|
K TTL REG DFF DFF8 3State
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS595
|
|
D 8 bits serial in // out Shift Register 3 State Out
|
|
K TTL SR 3State
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS596
|
|
D 8 bits serial in // out Shift Register Open Collect.
|
|
K HCMOS SR OpenCol
|
|
$ENDCMP
|
|
#
|
|
$CMP 74ls670
|
|
D 4 x 4 Register Files 3 State Out
|
|
K TTL Register 3State
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS688
|
|
D 8 bits Comparator
|
|
K TTL DECOD Arith
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS73
|
|
D Dual JK FlipFlop, reset
|
|
K TTL JK JKFF
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS74
|
|
D Dual D FlipFlop, Set & Reset
|
|
K TTL DFF
|
|
F 74xx/74hc_hct74.pdf
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS75
|
|
D 4 bits Latch
|
|
K TTL DFF Latch
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS76
|
|
D Dual JK FlipFlop, Set & Reset
|
|
K TTL JK JKFF
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS77
|
|
D 4 bits Latch
|
|
K TTL DFF Latch
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS78
|
|
D Dual JK FlipFlop, preset , common clock & reset
|
|
K TTL JK JKFF
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS83
|
|
D 4 bits Full Adder
|
|
K TTL ADD ARITH ALU
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS85
|
|
D 4 bits Comparateur
|
|
K TTL COMP ARITH
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS86
|
|
D Quad XOR 2 inputs
|
|
K TTL XOR2
|
|
F 74xx/74ls86.pdf
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS90
|
|
D BCD Counter ( div 2 & div 5 )
|
|
K TTL CNT CNT4
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS91
|
|
D 8 bits Serial Register
|
|
K TTL SR SR8
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS92
|
|
D Divide by 12 counter
|
|
K TTL CNT CNT4
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS93
|
|
D Divide by 2 & 8 counter
|
|
K TTL CNT CNT4
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LS95
|
|
D Shift Register 5 bits ( // in // out )
|
|
K TTL SR SR4
|
|
$ENDCMP
|
|
#
|
|
$CMP 74LV14
|
|
D Hex Inverseur
|
|
K TTL not inv
|
|
$ENDCMP
|
|
#
|
|
#End Doc Library
|