e92b21b43d
* reworked MAX77x (datasheet, symbol, missing variants, description ..) * reworked MC33063-family (symbol, missing variants, footprints, description, ...) * reworked MC34063 family as alias to MC33063 family * reworked MCP16301 (symbol, pin-type, description) * reworked MCP16311/2 (symbol, description, name without -, ...) * reworked MCP16331 (symbol, pin-type, naming without -...) * reworked MCP1640 family (symbol, naming wiothout -, ...) * corrected some descriptions * reworked MCP165x family (symbol, description) * reworked MIC2177 (datasheet, symbol, pin-stacks, description...) * added fixed-output variants of MIC2177 * added MIC2178 family * reworked MIC4690 (stacked-pins, symbol, description...) * reworked NID60-series (symbol, stacked-pins, footprint, FPFilter, description) added NID30-series (footprint available from https://github.com/KiCad/Converters_DCDC_ACDC.pretty/pull/25) * reworked NMAxxyyDC/SC-series (symbol, isolation bars, ...) * reworked NXE2-series (NC-pin location, description, ...) * reworked PAM2305 series (missing variants, symbols, description...) * removed very obsolete PT6100 (no footprint, no description available anymore ...) * reworked R-78E-series (description) * Added 3D models for ZETA-433-SO * Added Foot print name * Added Foot print name * reworked R78-Zxx-yy series from RECOM (symbol, added missing variants, footprints from https://github.com/KiCad/Converters_DCDC_ACDC.pretty/pull/26) * Updated description of 868 and 915 MHz * Made fields invisible * reworked ST1CC40 (symbol, package-variants, wrong pinout and package, description, ...) * Add Johansen chip antenna * Add symbol for MAX6971 LED driver. http://datasheets.maximintegrated.com/en/ds/MAX6971.pdf * Move Parallax Propeller to its own library. * The DIP version of the Propeller has two VDD pins and two VSS pins. * reworked ST1S10 family (footprints, description, symbols...) * reworked ST1S14PHR (symbol, missing PAD-pin, footprint, description, ...) * reworked Traco TEN20-series (symbol, isolation barrier, pin-position, description, ...) * reworked TL497 family (symbol, pin-types, description, FPFilters, ...) * reworked TMR_1 series (description...) * reworked TPS5431 (missing NCs, pin-types, description, footprint from https://github.com/KiCad/Housings_SOIC.pretty/pull/35...) * reworked TPS54340/TPS54360 (footprint, pin-types, description...) * reworked TPS560200 (description, ...) * reworked TPS56x200 (description, ...) * reworked TPS6050xDGS (pin-types, description, FPFilter, ...) * reworked TPS6120x (symbol, pin-location, description, footpritns, see https://github.com/KiCad/Housings_SON.pretty/pull/19) * reworked TPS621xy families (dscription, missing variants) * Removed Antenna.lib, added Antenna_Chip to device.lib * reworked TPS62xyz (missing variants, footprints, FPFilters, split by package, symbol, pin-types, description, ...) * added scripted Wuerth Mapi inductor models * reworked TPS6217xDQC (description, footprint from https://github.com/KiCad/Housings_SON.pretty/pull/20 ...) * added description to TPS62175DQC * reworked TPS6220xDBV (symbol, description, ...) * reworked TSR-1 series (description, symbol, ...) * fixed some KLC issues * reworked ADG729 * added ADG728 * removed CPC1017N which is already in opto.lib * Changed Antenna_Chip to use a resonator symbol * reworked DG308/DG309/DG441/DG442 * Fix naming for Schurter FUP 3d models. * Reduce pin length, text offset and body width of MCP45HVx1. * FRSolutions: Add the Particle P1 WiFi module * rfcom: Update footprint of ESP-12E * rfcom: Update footprint of ESP-12E * moved symbols from texas.lib and siliconi.lib to analog_switches.lib * Copy connector shape from USB_OTG to USB_B_Micro. I recently added the USB_B_Micro symbol (and an alias, USB_B_Mini). I hadn't noticed that there was already a similar USB_OTG symbol. However, the two need to remain separate, because USB_OTG has VBUS and GND marked as power inputs, while USB_B_Micro has them as power outputs. This commit makes USB_B_Micro identical to USB_OTG, except for the direction of the power pins. Specifically, it copies the connector shape from USB_OTG to USB_B_Micro. (I had been too lazy to draw the connector shape when I created USB_B_Micro.) * added missing NC-pins fixed naming added DG411/DG412/DG413 family * Added FAN3268 to ON Semiconductor library. * added DG417/DG418/DG419 and its variants ADG417/ADG419, MAX317/MAX318/MAX319 * corrected label location * Added 3D models for SW_SP3T_PCM13 and SW_SPDT_PCM12 * added DG417L/DG418L/DG419L fixed several minor issues (typos, wrong symbols, ...) * Combined bosch.lib and Bosch.lib * Don't update library version * RFSolutions: Rename P1 to Particle_P1 * LED: Add CLV1L-FKB * LED: CLV1L-FKB remove trademark symbol from description * fixed several swicthes (wrong normally settings) + added DG41x-variants from Maxim and other companies, as Maxim does not have the separate Vlogic pin! * added/reworked DG9421/DG9422 (package posted as https://github.com/KiCad/Housings_SSOP.pretty/pull/51) * reworked DG884 * Added name of package to description (FAN3268) * reworked FSA3157/NC7SB3157 (symbol, ...footprint from https://github.com/KiCad/Housings_SON.pretty/pull/21) * Update fp-lib-table.for-github * Update fp-lib-table.for-pretty * reworked TS5A3159/TS5A3160 (split by footprint, added missing variants, description, symbol, footprint from https://github.com/KiCad/Housings_BGA.pretty/pull/26) * rework HI524 (symbol, description, datasheet, footprint) * moved LCC110 to opto.lib and reworked symbol (footprint, symbol, ...) * moved LAA110, LB110 from analog_switches to opto.lib and reimplemented as ALIAS * added MAX312/313/314 family as ALIASes * added MAX323/324/325 series * fixed KLC issues (font-size, wrong FPFilters) * #IM fixed power-pin stack * update LTC2309 stack GND and VDD pins allowing for same schematic on both chips. Minor changes to adhere to KLC. * Added 3D models for dip switches * Updated according to PR feedback * Add TDA1308 Schematic library for the class-AB stereo headphone driver by NXP Signed-off-by: Adam Heinrich <adam@adamh.cz> * Rename Cortex Debug Connector, add FP filter - Renamed Cortex Debug Connector from `Conn_ARM_Cortex-Debug` to `CMP Conn_ARM_JTAG_SWD_10` - Added FP filter `Conn*:*_2x*` for KiCad v5 * Oscillators: Add SG3030CM * Removed CVS type * Removed CVS type * Updated leg and pad size * pspice: Add MOSFET symbols * Add cross 4p net tie * Add cross 4p net tie * Add symbol LED_BGRA. This is the pinout used by "Piranha" RGB LEDs. See that pull request for more information. * Add "LED*" footprint filter to LED symbols in "device" library. Also: * Added "~" datasheet to LED symbols to suppress KLC errors. * Corrected cases where fields 2 and 3 were not invisible. Did not attempt to correct other pre-existing KLC errors. (Pin placement.) * move symbol and package name, add potentiometer symbol inside. * Move footprint name more to the right. * Oscillators: Fix pin offset in SG-3030CM * Separate power pins on generic opamps * Update generic opamps symbols * Add x cap discharge ICs * Add x cap discharge ICs * Oscillators: Rename SG3030CM footprint to comply with KLC * Add TI OPA356 and OPA2356 operational amplifiers They use the same pinout as existing devices, so they are just new aliases. * Update atmel.lib * Added 3d part for Bosch LGA-8_2.5x2.5mm_Pitch0.65mm package, BME280 and BME680 * Corrected vent hole position, corrected marker pad position, pad numbering starts clockwise from right side * MCU_Texas_MSP430: fix G2553 * Update fp-lib-table.for-github * Update fp-lib-table.for-pretty * Update fp-lib-table.for-pretty * Update fp-lib-table.for-github * Add TI OPA1622 operational amplifier * - removed unneeded D-SUB 3D models - moved bornierXX 3D models * renamed bornier 3D models * - moved Phoenix 3D models to correct location * fixed D-SUB FPFilters for new footprints * revert DSUB-fixes (will do separately) * Added the Analog Devices ADP2302ARDZ * visual enhancements as requested * Added the Microchip MCP1825S 500mA LDO Regulator * Update net ties * Update net ties * Fixed keywords, modified pin name offset, fixed pin type (FAN3268). * Clearing an error in STM32L071/STM32L072 loading libs * Add PD70224 * Add PD70224 * Fixed dot location * Add "T" 3-pin net tie * Add "T" 3-pin net tie * Remove duplicated polylines in net ties * Removed the errored lines altogether. * Add OPA890 operational amplifier in SOT23-6 package * Add Allegro current sensors * Updated sym_lib_table file * Added TJA1052i * Added Alias Alias for different isolation voltages * Set pointing * Added isolation lines * Replaced illegal character * fix sym-lib-table typos ang missing Logic_ prefixes * added LSM303C and LSM6DS3 * Fix footprint filter * hopefully final fixups * MCU_Texas_MSP430: update keywords * MCU_Texas_MSP430: update description - do not duplicate part name (KLC 3.0.2 S6.3) - append simplified footprint name (KLC 3.0.2 S6.3) * MCU_Texas_MSP430: update documentation file Always use a symlink based on the actual part number, even if multiple devices share the same data sheet. * Added better descriptions for symbol libraries * Add TPS2592xx Schematic library for the 5V/12V eFuse protection switch by TI Signed-off-by: Adam Heinrich <adam@adamh.cz> * Moved nc pins and made them visible * Fixed Stacking & Naming * Add TPS22929D power distribution switch * - adjusted names of the symbols to the new KLC * Added TPS61090, TPS61091, and TPS61092 boost converters. * added TPD3E001DRLR TPD2E2U06 * updated to resolve jenkins issues * Updated to address automated script issues * Fixed additional errors * Fixed ground pin alignment * Updated footprint * Microchip: SY89312V 3.3/5V, ECL/PECL 4GHz x2 clock divider Documentation: http://ww1.microchip.com/downloads/en/DeviceDoc/sy89312v.pdf * fixed library version to make these workable with KiCAD 4.0.7 (see https://github.com/KiCad/kicad-library/issues/1838) * removed whiteline that lead to error * changed model name as per footprint, rotated 90 degree CCW, ofset 0,0,0 * Add Analog Devices ADP5070/5071 switching regulators * Adjusted the PIC12 symbol names to the new KLC * Changed pin order * fixed several issues in transistors.lib/dcm: - unified naming/description - fixed some packages (e.g. TO-220-variants had wrong names) - fixed wrong BF245/244 symbols (https://github.com/KiCad/kicad-library/issues/1843#issuecomment-345438714) - added BF545 - added some missing datasheets * Removed unnecessary changes to rest of the file * - removed non-existent device from DCM (that device really is not produced!) - fixed one description (package type) * Update .travis.yml Remove sudo requirement
320 lines
13 KiB
Text
320 lines
13 KiB
Text
(kicad_pcb (version 4) (host pcbnew 4.0.5)
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(general
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(links 0)
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(no_connects 0)
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(area 143.424999 124.924999 228.575001 181.075001)
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(thickness 1.6)
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(drawings 41)
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(tracks 0)
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(zones 0)
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(modules 1)
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(nets 27)
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)
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(page A3)
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(title_block
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(date "15 nov 2012")
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)
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(layers
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(0 F.Cu signal)
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(31 B.Cu signal)
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(32 B.Adhes user)
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(33 F.Adhes user)
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(34 B.Paste user)
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(35 F.Paste user)
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(36 B.SilkS user)
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(37 F.SilkS user)
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(38 B.Mask user)
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(39 F.Mask user)
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(40 Dwgs.User user)
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(41 Cmts.User user)
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(42 Eco1.User user)
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(43 Eco2.User user)
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(44 Edge.Cuts user)
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)
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(setup
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(last_trace_width 0.2)
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(trace_clearance 0.2)
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(zone_clearance 0.508)
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(zone_45_only no)
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(trace_min 0.1524)
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(segment_width 0.2)
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(edge_width 0.15)
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(via_size 0.9)
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(via_drill 0.6)
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(via_min_size 0.8)
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(via_min_drill 0.5)
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(uvia_size 0.5)
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(uvia_drill 0.1)
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(uvias_allowed no)
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(uvia_min_size 0.5)
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(uvia_min_drill 0.1)
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(pcb_text_width 0.3)
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(pcb_text_size 1 1)
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(mod_edge_width 0.15)
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(mod_text_size 1 1)
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(mod_text_width 0.15)
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(pad_size 1 1)
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(pad_drill 0.6)
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(pad_to_mask_clearance 0)
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(aux_axis_origin 143.5 181)
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(visible_elements 7FFFFFFF)
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(pcbplotparams
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(layerselection 0x00030_80000001)
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(usegerberextensions true)
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(excludeedgelayer true)
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(linewidth 0.150000)
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(plotframeref false)
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(viasonmask false)
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(mode 1)
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(useauxorigin false)
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(hpglpennumber 1)
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(hpglpenspeed 20)
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(hpglpendiameter 15)
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(hpglpenoverlay 2)
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(psnegative false)
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(psa4output false)
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(plotreference true)
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(plotvalue true)
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(plotinvisibletext false)
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(padsonsilk false)
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(subtractmaskfromsilk false)
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(outputformat 1)
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(mirror false)
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(drillshape 1)
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(scaleselection 1)
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(outputdirectory ""))
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)
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(net 0 "")
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(net 1 +5V)
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(net 2 GND)
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(net 3 +3V3)
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(net 4 "/GPIO0(SDA)")
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(net 5 "Net-(P1-Pad4)")
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(net 6 "/GPIO1(SCL)")
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(net 7 /GPIO4)
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(net 8 /TXD)
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(net 9 "Net-(P1-Pad9)")
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(net 10 /RXD)
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(net 11 /GPIO17)
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(net 12 /GPIO18)
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(net 13 /GPIO21)
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(net 14 "Net-(P1-Pad14)")
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(net 15 /GPIO22)
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(net 16 /GPIO23)
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(net 17 "Net-(P1-Pad17)")
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(net 18 /GPIO24)
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(net 19 "/GPIO10(MOSI)")
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(net 20 "Net-(P1-Pad20)")
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(net 21 "/GPIO9(MISO)")
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(net 22 /GPIO25)
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(net 23 "/GPIO11(SCLK)")
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(net 24 "/GPIO8(CE0)")
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(net 25 "Net-(P1-Pad25)")
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(net 26 "/GPIO7(CE1)")
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(net_class Default "This is the default net class."
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(clearance 0.2)
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(trace_width 0.2)
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(via_dia 0.9)
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(via_drill 0.6)
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(uvia_dia 0.5)
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(uvia_drill 0.1)
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(add_net +3V3)
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(add_net +5V)
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(add_net "/GPIO0(SDA)")
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(add_net "/GPIO1(SCL)")
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(add_net "/GPIO10(MOSI)")
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(add_net "/GPIO11(SCLK)")
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(add_net /GPIO17)
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(add_net /GPIO18)
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(add_net /GPIO21)
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(add_net /GPIO22)
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(add_net /GPIO23)
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(add_net /GPIO24)
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(add_net /GPIO25)
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(add_net /GPIO4)
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(add_net "/GPIO7(CE1)")
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(add_net "/GPIO8(CE0)")
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(add_net "/GPIO9(MISO)")
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(add_net /RXD)
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(add_net /TXD)
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(add_net GND)
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(add_net "Net-(P1-Pad14)")
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(add_net "Net-(P1-Pad17)")
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(add_net "Net-(P1-Pad20)")
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(add_net "Net-(P1-Pad25)")
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(add_net "Net-(P1-Pad4)")
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(add_net "Net-(P1-Pad9)")
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)
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(net_class Power ""
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(clearance 0.2)
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(trace_width 0.5)
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(via_dia 1)
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(via_drill 0.7)
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(uvia_dia 0.5)
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(uvia_drill 0.1)
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)
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(module Pin_Headers:Pin_Header_Straight_2x13 locked (layer F.Cu) (tedit 584FB37B) (tstamp 584FB325)
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(at 145.75536 130.27914 90)
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(descr "Through hole pin header")
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(tags "pin header")
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(path /50A55ABA)
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(fp_text reference P1 (at 1.5875 32.6136 90) (layer F.SilkS)
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_text value CONN_13X2 (at -2.37998 16.29664 180) (layer F.Fab)
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_line (start -1.75 -1.75) (end -1.75 32.25) (layer F.CrtYd) (width 0.05))
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(fp_line (start 4.3 -1.75) (end 4.3 32.25) (layer F.CrtYd) (width 0.05))
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(fp_line (start -1.75 -1.75) (end 4.3 -1.75) (layer F.CrtYd) (width 0.05))
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(fp_line (start -1.75 32.25) (end 4.3 32.25) (layer F.CrtYd) (width 0.05))
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(fp_line (start 3.81 -1.27) (end 3.81 31.75) (layer F.SilkS) (width 0.15))
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(fp_line (start -1.27 1.27) (end -1.27 31.75) (layer F.SilkS) (width 0.15))
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(fp_line (start 3.81 31.75) (end -1.27 31.75) (layer F.SilkS) (width 0.15))
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(fp_line (start 3.81 -1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15))
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(fp_line (start 0 -1.55) (end -1.55 -1.55) (layer F.SilkS) (width 0.15))
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(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.15))
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(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15))
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(fp_line (start -1.55 -1.55) (end -1.55 0) (layer F.SilkS) (width 0.15))
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(pad 1 thru_hole rect (at 0 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 3 +3V3))
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(pad 2 thru_hole oval (at 2.54 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 1 +5V))
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(pad 3 thru_hole oval (at 0 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 4 "/GPIO0(SDA)"))
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(pad 4 thru_hole oval (at 2.54 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 5 "Net-(P1-Pad4)"))
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(pad 5 thru_hole oval (at 0 5.08 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 6 "/GPIO1(SCL)"))
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(pad 6 thru_hole oval (at 2.54 5.08 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 2 GND))
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(pad 7 thru_hole oval (at 0 7.62 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 7 /GPIO4))
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(pad 8 thru_hole oval (at 2.54 7.62 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 8 /TXD))
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(pad 9 thru_hole oval (at 0 10.16 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 9 "Net-(P1-Pad9)"))
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(pad 10 thru_hole oval (at 2.54 10.16 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 10 /RXD))
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(pad 11 thru_hole oval (at 0 12.7 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 11 /GPIO17))
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(pad 12 thru_hole oval (at 2.54 12.7 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 12 /GPIO18))
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(pad 13 thru_hole oval (at 0 15.24 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 13 /GPIO21))
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(pad 14 thru_hole oval (at 2.54 15.24 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 14 "Net-(P1-Pad14)"))
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(pad 15 thru_hole oval (at 0 17.78 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 15 /GPIO22))
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(pad 16 thru_hole oval (at 2.54 17.78 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 16 /GPIO23))
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(pad 17 thru_hole oval (at 0 20.32 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 17 "Net-(P1-Pad17)"))
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(pad 18 thru_hole oval (at 2.54 20.32 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 18 /GPIO24))
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(pad 19 thru_hole oval (at 0 22.86 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 19 "/GPIO10(MOSI)"))
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(pad 20 thru_hole oval (at 2.54 22.86 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 20 "Net-(P1-Pad20)"))
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(pad 21 thru_hole oval (at 0 25.4 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 21 "/GPIO9(MISO)"))
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(pad 22 thru_hole oval (at 2.54 25.4 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 22 /GPIO25))
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(pad 23 thru_hole oval (at 0 27.94 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 23 "/GPIO11(SCLK)"))
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(pad 24 thru_hole oval (at 2.54 27.94 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 24 "/GPIO8(CE0)"))
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(pad 25 thru_hole oval (at 0 30.48 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 25 "Net-(P1-Pad25)"))
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(pad 26 thru_hole oval (at 2.54 30.48 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 26 "/GPIO7(CE1)"))
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(model Pin_Headers.3dshapes/Pin_Header_Straight_2x13.wrl
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(at (xyz 0.05 -0.6 0))
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(scale (xyz 1 1 1))
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(effects (font (size 2 1.7) (thickness 0.12)) (justify left))
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)
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(gr_text "56.000 mm" (at 132 153 90) (layer Dwgs.User)
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(gr_text "85.000 mm" (at 186 113.000001) (layer Dwgs.User)
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(gr_text "RCA\nREMOVE WITH\nSTD HEADERS\n!NO TH ABOVE!" (at 188.5 118) (layer Dwgs.User)
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(effects (font (size 1 1) (thickness 0.12)))
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)
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(gr_text "1/8\" JACK\nOK WITH STD\nHEADERS\n!NO TH ABOVE!" (at 207.5 118) (layer Dwgs.User)
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(gr_line (start 228.5 181) (end 228.5 157) (angle 90) (layer Edge.Cuts) (width 0.15))
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(gr_text "DOUBLE USB\nCUTOUT FOR ALL\nBOARDS" (at 236.5 149) (layer Dwgs.User)
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(gr_text "RJ45\nCUTOUT FOR STD\nHEADERS\n!NO TH ABOVE!" (at 236.5 170) (layer Dwgs.User)
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