374 lines
13 KiB
Plaintext
374 lines
13 KiB
Plaintext
(kicad_pcb (version 3) (host pcbnew "(2013-02-23 BZR 3971)-testing")
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(general
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(links 3)
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(area 32.945069 34.215069 76.274931 118.819931)
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(thickness 1.6002)
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(page A3)
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(title_block
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(title "STM32 Value Line Discovery - Shiled board")
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(rev 1.0)
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(layers
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(15 Front signal)
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(27 Eco2.User user)
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(28 Contours.Ci user)
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(setup
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(net 3 GND)
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(net_class Default "To jest domyślna klasa połączeń."
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(clearance 0.254)
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(module PIN_ARRAY_6X1 locked (layer Front) (tedit 50827C81) (tstamp 50827C60)
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(at 55.88 113.03)
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(descr "Single rangee contacts 1 x 6 pins")
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(tags CONN)
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(module PIN_ARRAY_28X1 locked (layer Front) (tedit 50827C6F) (tstamp 50827C84)
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(at 39.37 73.66 270)
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(descr "Single rangee contacts 1 x 28 pins")
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(tags CONN)
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(module PIN_ARRAY_28X1 locked (layer Front) (tedit 50827C8E) (tstamp 50827CA8)
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(at 69.85 73.66 90)
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(descr "Single rangee contacts 1 x 28 pins")
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(tags CONN)
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