ea81d981e3
- Applying KLC Rules (pin aligment, update text height) - Update some of documentation fields - Fix AD9891 wrong data port pinning
27 lines
675 B
Plaintext
27 lines
675 B
Plaintext
EESchema-DOCLIB Version 2.0
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#
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$CMP AD9891
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D AD9891, CCD Signal Processor, 20MHz 10bits, CSPBGA-64
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K CCD Signal Processor
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F http://www.analog.com/static/imported-files/data_sheets/AD9891_9895.pdf
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$ENDCMP
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$CMP AD9895
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D AD9895, CCD Signal Processor, 30MHz 12bits, CSPBGA-64
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K CCD Signal Processor
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F http://www.analog.com/static/imported-files/data_sheets/AD9891_9895.pdf
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$ENDCMP
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#
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$CMP CXD3400N
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D CXD3400N, 6-channel Vertical Clock Driver for CCD Image Sensor, SSOP-20
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K CCD Clock Driver
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F video\cxd3400n.pdf
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$ENDCMP
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$CMP ICX415AQ
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D ICX415AQ, Diagonal 8mm B/W Progressive Scan CCD Image Sensor with Square Pixel, CERDIP-22
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K CCD B/W Image Sensor
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$ENDCMP
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#End Doc Library
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