671 lines
45 KiB
Plaintext
671 lines
45 KiB
Plaintext
EESchema-LIBRARY Version 2.3 Date: Mon 13 Aug 2012 11:03:03 PM PET
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#encoding utf-8
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#
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# STM32F405VG
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#
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DEF STM32F405VG U 0 40 Y Y 1 F N
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F0 "U" 0 0 60 H V C CNN
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F1 "STM32F405VG" 0 100 60 H V C CNN
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F2 "TQFP100" 0 -100 60 H V C CNN
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DRAW
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S -4700 -2700 4700 2700 0 1 0 f
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X PE2/TRACECLK/FSMC_A23/EVENTOUT 1 5000 2350 300 L 50 50 1 1 I
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X PE3/TRACED0/FSMC_A19/EVENTOUT 2 5000 2250 300 L 50 50 1 1 I
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X PE4/TRACED1/FSMC_A20/EVENTOUT 3 5000 2150 300 L 50 50 1 1 I
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X PE5/TRACED2/FSMC_A21/TIM9_CH1/EVENTOUT 4 5000 2050 300 L 50 50 1 1 I
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X PE6/TRACED3_/_FSMC_A22/TIM9_CH2/EVENTOUT 5 5000 1950 300 L 50 50 1 1 I
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X VBAT 6 1250 3000 300 D 50 50 1 1 I
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X PC13/EVENTOUT 7 5000 -2350 300 L 50 50 1 1 I
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X PC14/OSC32_IN/EVENTOUT 8 5000 -2450 300 L 50 50 1 1 I
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X PC15/OSC32_OUT/EVENTOUT 9 5000 -2550 300 L 50 50 1 1 I
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X VSS 10 -200 -3000 300 U 50 50 1 1 I
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X VSSA 20 -400 -3000 300 U 50 50 1 1 I
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X PA5/SPI1_SCK/OTG_HS_ULPI_CK/TIM2_CH1_ETR/TIM8_CHIN/EVENTOUT 30 -5000 250 300 R 50 50 1 1 I
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X PE9/FSMC_D6/TIM1_CH1/EVENTOUT 40 5000 1650 300 L 50 50 1 1 I
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X VDD 50 150 3000 300 D 50 50 1 1 I
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X PD13/FSMC_A18/TIM4_CH2/EVENTOUT 60 5000 -550 300 L 50 50 1 1 I
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X PA11/USART1_CTS/CAN1_RX/TIM1_CH4_/OTG_FS_DM/EVENTOUT 70 -5000 -350 300 R 50 50 1 1 I
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X PC12/UART5_TX/SDIO_CK/SPI3_MOSI/I2S3_SD/USART3_CK/EVENTOUT 80 5000 -2250 300 L 50 50 1 1 I
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X PB4/NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD/EVENTOUT 90 -5000 -1450 300 R 50 50 1 1 I
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X VDD 11 -750 3000 300 D 50 50 1 1 I
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X VREF+ 21 -2250 3000 300 D 50 50 1 1 I
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X PA6/SPI1_MISO/TIM8_BKIN/TIM13_CH1/TIM3_CH1/TIM1_BKIN/EVENTOUT 31 -5000 150 300 R 50 50 1 1 I
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X PE10/FSMC_D7/TIM1_CH2N/EVENTOUT 41 5000 1550 300 L 50 50 1 1 I
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X PB12/SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN/CAN2_RX/OTG_HS_ULPI_D5/OTG_HS_ID/EVENTOUT 51 -5000 -2250 300 R 50 50 1 1 I
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X PD14/FSMC_D0/TIM4_CH3/EVENTOUT/_EVENTOUT 61 5000 -650 300 L 50 50 1 1 I
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X PA12/USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP/EVENTOUT 71 -5000 -450 300 R 50 50 1 1 I
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X PD0/FSMC_D2/CAN1_RX/EVENTOUT 81 5000 750 300 L 50 50 1 1 I
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X PB5/I2C1_SMBA/CAN2_RX/OTG_HS_ULPI_D7/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/I2S3_SD/EVENTOUT 91 -5000 -1550 300 R 50 50 1 1 I
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X PH0/OSC_IN/EVENTOUT 12 -5000 2150 300 R 50 50 1 1 I
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X VDDA 22 -1750 3000 300 D 50 50 1 1 I
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X PA7/SPI1_MOSI/TIM8_CH1N/TIM14_CH1/TIM3_CH2/TIM1_CH1N/EVENTOUT 32 -5000 50 300 R 50 50 1 1 I
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X PE11/FSMC_D8/TIM1_CH2/EVENTOUT 42 5000 1450 300 L 50 50 1 1 I
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X PB13/SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N/CAN2_TX/OTG_HS_ULPI_D6/EVENTOUT 52 -5000 -2350 300 R 50 50 1 1 I
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X PD15/FSMC_D1/TIM4_CH4/EVENTOUT 62 5000 -750 300 L 50 50 1 1 I
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X PA13/JTMS/SWDIO/EVENTOUT 72 -5000 -550 300 R 50 50 1 1 I
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X PD1/FSMC_D3/CAN1_TX/EVENTOUT 82 5000 650 300 L 50 50 1 1 I
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X PB6/I2C1_SCL/TIM4_CH1/CAN2_TX/USART1_TX/EVENTOUT 92 -5000 -1650 300 R 50 50 1 1 I
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X PH1/OSC_OUT/EVENTOUT 13 -5000 1550 300 R 50 50 1 1 I
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X PA0/WKUP/USART2_CTS/UART4_TX/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR/EVENTOUT 23 -5000 750 300 R 50 50 1 1 I
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X PC4/EVENTOUT 33 5000 -1450 300 L 50 50 1 1 I
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X PE12/FSMC_D9/TIM1_CH3N/EVENTOUT 43 5000 1350 300 L 50 50 1 1 I
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X PB14/SPI2_MISO/TIM1_CH2N/TIM12_CH1/OTG_HS_DM/USART3_RTS/TIM8_CH2N/I2S2ext_SD/EVENTOUT 53 -5000 -2450 300 R 50 50 1 1 I
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X PC6/I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/TIM3_CH1/EVENTOUT 63 5000 -1650 300 L 50 50 1 1 I
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X VCAP_2 73 1400 -3000 300 U 50 50 1 1 I
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X PD2/TIM3_ETR/UART5_RX/SDIO_CMD/EVENTOUT 83 5000 550 300 L 50 50 1 1 I
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X PB7/I2C1_SDA/FSMC_NL/USART1_RX/TIM4_CH2/EVENTOUT 93 -5000 -1750 300 R 50 50 1 1 I
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X NRST 14 -5000 2350 300 R 50 50 1 1 I
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X PA1/USART2_RTS/UART4_RX/TIM5_CH2/TIMM2_CH2/EVENTOUT 24 -5000 650 300 R 50 50 1 1 I
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X PC5/EVENTOUT 34 5000 -1550 300 L 50 50 1 1 I
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X PE13/FSMC_D10/TIM1_CH3/EVENTOUT 44 5000 1250 300 L 50 50 1 1 I
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X PB15/SPI2_MOSI/I2S2_SD/TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP/EVENTOUT 54 -5000 -2550 300 R 50 50 1 1 I
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X PC7/I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/TIM3_CH2/EVENTOUT 64 5000 -1750 300 L 50 50 1 1 I
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X VSS 74 200 -3000 300 U 50 50 1 1 I
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X PD3/FSMC_CLK/USART2_CTS/EVENTOUT 84 5000 450 300 L 50 50 1 1 I
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X BOOT0 94 -5000 2550 300 R 50 50 1 1 I
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X PC0/OTG_HS_ULPI_STP/EVENTOUT 15 5000 -1050 300 L 50 50 1 1 I
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X PA2/USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3/EVENTOUT 25 -5000 550 300 R 50 50 1 1 I
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X PB0/TIM3_CH3/TIM8_CH2N/OTG_HS_ULPI_D1/TIM1_CH2N/EVENTOUT 35 -5000 -1050 300 R 50 50 1 1 I
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X PE14/FSMC_D11/TIM1_CH4/EVENTOUT 45 5000 1150 300 L 50 50 1 1 I
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X PD8/FSMC_D13/USART3_TX/EVENTOUT 55 5000 -50 300 L 50 50 1 1 I
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X PC8/TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK/EVENTOUT 65 5000 -1850 300 L 50 50 1 1 I
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X VDD 75 450 3000 300 D 50 50 1 1 I
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X PD4/FSMC_NOE/USART2_RTS/EVENTOUT 85 5000 350 300 L 50 50 1 1 I
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X PB8/TIM4_CH3/SDIO_D4/TIM10_CH1/I2C1_SCL/CAN1_RX/EVENTOUT 95 -5000 -1850 300 R 50 50 1 1 I
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X PC1/_EVENTOUT 16 5000 -1150 300 L 50 50 1 1 I
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X PA3/USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/OTG_HS_ULPI_D0/EVENTOUT 26 -5000 450 300 R 50 50 1 1 I
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X PB1/TIM3_CH4/TIM8_CH3N/OTG_HS_ULPI_D2/OTG_HS_INTN/TIM1_CH3N/EVENTOUT 36 -5000 -1150 300 R 50 50 1 1 I
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X PE15/FSMC_D12/TIM1_BKIN/EVENTOUT 46 5000 1050 300 L 50 50 1 1 I
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X PD9/FSMC_D14/USART3_RX/EVENTOUT 56 5000 -150 300 L 50 50 1 1 I
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X PC9/I2S_CKIN/MCO2/TIM8_CH4/SDIO_D1/I2C3_SDA/TIM3_CH4/EVENTOUT 66 5000 -1950 300 L 50 50 1 1 I
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X PA14/JTCK/SWCLK/EVENTOUT 76 -5000 -650 300 R 50 50 1 1 I
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X PD5/FSMC_NWE/USART2_TX/EVENTOUT 86 5000 250 300 L 50 50 1 1 I
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X PB9/SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/I2C1_SDA/CAN1_TX/EVENTOUT 96 -5000 -1950 300 R 50 50 1 1 I
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X PC2/SPI2_MISO/OTG_HS_ULPI_DIR/I2S2ext_SD/EVENTOUT 17 5000 -1250 300 L 50 50 1 1 I
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X VSS 27 0 -3000 300 U 50 50 1 1 I
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X PB2/BOOT1/EVENTOUT 37 -5000 -1250 300 R 50 50 1 1 I
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X PB10/SPI2_SCK/I2S2_CK/I2C2_SCL/USART3_TX/OTG_HS_ULPI_D3/TIM2_CH3/EVENTOUT 47 -5000 -2050 300 R 50 50 1 1 I
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X PD10/FSMC_D15/USART3_CK/EVENTOUT 57 5000 -250 300 L 50 50 1 1 I
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X PA8/MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF/EVENTOUT 67 -5000 -50 300 R 50 50 1 1 I
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X PA15/JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS/EVENTOUT 77 -5000 -750 300 R 50 50 1 1 I
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X PD6/FSMC_NWAIT/USART2_RX/EVENTOUT 87 5000 150 300 L 50 50 1 1 I
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X PE0/TIM4_ETR/FSMC_NBL0/EVENTOUT 97 5000 2550 300 L 50 50 1 1 I
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X PC3/SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT/EVENTOUT 18 5000 -1350 300 L 50 50 1 1 I
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X VDD 28 -150 3000 300 D 50 50 1 1 I
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X PE7/FSMC_D4/TIM1_ETR/EVENTOUT 38 5000 1850 300 L 50 50 1 1 I
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X PB11/I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4/TIM2_CH4/EVENTOUT 48 -5000 -2150 300 R 50 50 1 1 I
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X PD11/FSMC_CLE/FSMC_A16/USART3_CTS/EVENTOUT 58 5000 -350 300 L 50 50 1 1 I
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X PA9/USART1_TX/TIM1_CH2/I2C3_SMBA/EVENTOUT 68 -5000 -150 300 R 50 50 1 1 I
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X PC10/SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/USART3_TX/EVENTOUT 78 5000 -2050 300 L 50 50 1 1 I
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X PD7/USART2_CK/FSMC_NE1/FSMC_NCE2/EVENTOUT 88 5000 50 300 L 50 50 1 1 I
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X PE1/FSMC_NBL1/EVENTOUT 98 5000 2450 300 L 50 50 1 1 I
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X VDD 19 -450 3000 300 D 50 50 1 1 I
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X PA4/SPI1_NSS/SPI3_NSS/USART2_CK/OTG_HS_SOF/I2S3_WS/EVENTOUT 29 -5000 350 300 R 50 50 1 1 I
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X PE8/FSMC_D5/TIM1_CH1N/EVENTOUT 39 5000 1750 300 L 50 50 1 1 I
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X VCAP_1 49 900 -3000 300 U 50 50 1 1 I
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X PD12/FSMC_ALE/FSMC_A17/TIM4_CH1/USART3_RTS/EVENTOUT 59 5000 -450 300 L 50 50 1 1 I
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X PA10/USART1_RX/TIM1_CH3/OTG_FS_ID/EVENTOUT 69 -5000 -250 300 R 50 50 1 1 I
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X PC11/UART4_RX/SPI3_MISO/SDIO_D3/USART3_RX/I2S3ext_SD/EVENTOUT 79 5000 -2150 300 L 50 50 1 1 I
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X PB3/JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK/EVENTOUT 89 -5000 -1350 300 R 50 50 1 1 I
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X VSS 99 400 -3000 300 U 50 50 1 1 I
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X VDD 100 750 3000 300 D 50 50 1 1 I
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ENDDRAW
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ENDDEF
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#
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# STM32F407VE
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#
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DEF STM32F407VE U 0 40 Y Y 1 F N
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F0 "U" 0 0 60 H V C CNN
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F1 "STM32F407VE" 0 100 60 H V C CNN
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F2 "TQFP100" 0 -100 60 H V C CNN
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DRAW
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S -4700 -2700 4700 2700 0 1 0 f
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X PE2/TRACECLK/FSMC_A23/ETH_MII_TXD3/EVENTOUT 1 5000 2350 300 L 50 50 1 1 I
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X PE3/TRACED0/FSMC_A19/EVENTOUT 2 5000 2250 300 L 50 50 1 1 I
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X PE4/TRACED1/FSMC_A20/DCMI_D4/EVENTOUT 3 5000 2150 300 L 50 50 1 1 I
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X PE5/TRACED2/FSMC_A21/TIM9_CH1/DCMI_D6/EVENTOUT 4 5000 2050 300 L 50 50 1 1 I
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X PE6/TRACED3_/_FSMC_A22/TIM9_CH2/DCMI_D7/EVENTOUT 5 5000 1950 300 L 50 50 1 1 I
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X VBAT 6 1250 3000 300 D 50 50 1 1 I
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X PC13/EVENTOUT 7 5000 -2350 300 L 50 50 1 1 I
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X PC14/OSC32_IN/EVENTOUT 8 5000 -2450 300 L 50 50 1 1 I
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X PC15/OSC32_OUT/EVENTOUT 9 5000 -2550 300 L 50 50 1 1 I
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X VSS 10 -200 -3000 300 U 50 50 1 1 I
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X VSSA 20 -400 -3000 300 U 50 50 1 1 I
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X PA5/SPI1_SCK/OTG_HS_ULPI_CK/TIM2_CH1_ETR/TIM8_CHIN/EVENTOUT 30 -5000 250 300 R 50 50 1 1 I
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X PE9/FSMC_D6/TIM1_CH1/EVENTOUT 40 5000 1650 300 L 50 50 1 1 I
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X VDD 50 150 3000 300 D 50 50 1 1 I
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X PD13/FSMC_A18/TIM4_CH2/EVENTOUT 60 5000 -550 300 L 50 50 1 1 I
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X PA11/USART1_CTS/CAN1_RX/TIM1_CH4_/OTG_FS_DM/EVENTOUT 70 -5000 -350 300 R 50 50 1 1 I
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X PC12/UART5_TX/SDIO_CK/DCMI_D9/SPI3_MOSI/I2S3_SD/USART3_CK/EVENTOUT 80 5000 -2250 300 L 50 50 1 1 I
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X PB4/NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD/EVENTOUT 90 -5000 -1450 300 R 50 50 1 1 I
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X VDD 11 -750 3000 300 D 50 50 1 1 I
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X VREF+ 21 -2250 3000 300 D 50 50 1 1 I
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X PA6/SPI1_MISO/TIM8_BKIN/TIM13_CH1/DCMI_PIXCLK/TIM3_CH1/TIM1_BKIN/EVENTOUT 31 -5000 150 300 R 50 50 1 1 I
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X PE10/FSMC_D7/TIM1_CH2N/EVENTOUT 41 5000 1550 300 L 50 50 1 1 I
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X PB12/SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN/CAN2_RX/OTG_HS_ULPI_D5/ETH_RMII_TXD0/ETH_MII_TXD0/OTG_HS_ID/EVENTOUT 51 -5000 -2250 300 R 50 50 1 1 I
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X PD14/FSMC_D0/TIM4_CH3/EVENTOUT/_EVENTOUT 61 5000 -650 300 L 50 50 1 1 I
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X PA12/USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP/EVENTOUT 71 -5000 -450 300 R 50 50 1 1 I
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X PD0/FSMC_D2/CAN1_RX/EVENTOUT 81 5000 750 300 L 50 50 1 1 I
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X PB5/I2C1_SMBA/CAN2_RX/OTG_HS_ULPI_D7/ETH_PPS_OUT/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/DCMI_D10/I2S3_SD/EVENTOUT 91 -5000 -1550 300 R 50 50 1 1 I
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X PH0/OSC_IN/EVENTOUT 12 -5000 2150 300 R 50 50 1 1 I
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X VDDA 22 -1750 3000 300 D 50 50 1 1 I
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X PA7/SPI1_MOSI/TIM8_CH1N/TIM14_CH1/TIM3_CH2/ETH_MII_RX_DV/TIM1_CH1N/RMII_CRS_DV/EVENTOUT 32 -5000 50 300 R 50 50 1 1 I
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X PE11/FSMC_D8/TIM1_CH2/EVENTOUT 42 5000 1450 300 L 50 50 1 1 I
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X PB13/SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N/CAN2_TX/OTG_HS_ULPI_D6/ETH_RMII_TXD1/ETH_MII_TXD1/EVENTOUT 52 -5000 -2350 300 R 50 50 1 1 I
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X PD15/FSMC_D1/TIM4_CH4/EVENTOUT 62 5000 -750 300 L 50 50 1 1 I
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X PA13/JTMS/SWDIO/EVENTOUT 72 -5000 -550 300 R 50 50 1 1 I
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X PD1/FSMC_D3/CAN1_TX/EVENTOUT 82 5000 650 300 L 50 50 1 1 I
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X PB6/I2C1_SCL/TIM4_CH1/CAN2_TX/DCMI_D5/USART1_TX/EVENTOUT 92 -5000 -1650 300 R 50 50 1 1 I
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X PH1/OSC_OUT/EVENTOUT 13 -5000 1550 300 R 50 50 1 1 I
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X PA0/WKUP/USART2_CTS/UART4_TX/ETH_MII_CRS_/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR/EVENTOUT 23 -5000 750 300 R 50 50 1 1 I
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X PC4/ETH_RMII_RX_D0/ETH_MII_RX_D0/EVENTOUT 33 5000 -1450 300 L 50 50 1 1 I
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X PE12/FSMC_D9/TIM1_CH3N/EVENTOUT 43 5000 1350 300 L 50 50 1 1 I
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X PB14/SPI2_MISO/TIM1_CH2N/TIM12_CH1/OTG_HS_DM/USART3_RTS/TIM8_CH2N/I2S2ext_SD/EVENTOUT 53 -5000 -2450 300 R 50 50 1 1 I
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X PC6/I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/DCMI_D0/TIM3_CH1/EVENTOUT 63 5000 -1650 300 L 50 50 1 1 I
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X VCAP_2 73 1400 -3000 300 U 50 50 1 1 I
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X PD2/TIM3_ETR/UART5_RX/SDIO_CMD/DCMI_D11/EVENTOUT 83 5000 550 300 L 50 50 1 1 I
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X PB7/I2C1_SDA/FSMC_NL/DCMI_VSYNC/USART1_RX/TIM4_CH2/EVENTOUT 93 -5000 -1750 300 R 50 50 1 1 I
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X NRST 14 -5000 2350 300 R 50 50 1 1 I
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X PA1/USART2_RTS/UART4_RX/ETH_RMII_REF_CLK/ETH_MII_RX_CLK/TIM5_CH2/TIMM2_CH2/EVENTOUT 24 -5000 650 300 R 50 50 1 1 I
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X PC5/ETH_RMII_RX_D1/ETH_MII_RX_D1/EVENTOUT 34 5000 -1550 300 L 50 50 1 1 I
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X PE13/FSMC_D10/TIM1_CH3/EVENTOUT 44 5000 1250 300 L 50 50 1 1 I
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X PB15/SPI2_MOSI/I2S2_SD/TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP/EVENTOUT 54 -5000 -2550 300 R 50 50 1 1 I
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X PC7/I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/DCMI_D1/TIM3_CH2/EVENTOUT 64 5000 -1750 300 L 50 50 1 1 I
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X VSS 74 200 -3000 300 U 50 50 1 1 I
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X PD3/FSMC_CLK/USART2_CTS/EVENTOUT 84 5000 450 300 L 50 50 1 1 I
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X BOOT0 94 -5000 2550 300 R 50 50 1 1 I
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X PC0/OTG_HS_ULPI_STP/EVENTOUT 15 5000 -1050 300 L 50 50 1 1 I
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X PA2/USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3/ETH_MDIO/EVENTOUT 25 -5000 550 300 R 50 50 1 1 I
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X PB0/TIM3_CH3/TIM8_CH2N/OTG_HS_ULPI_D1/ETH_MII_RXD2/TIM1_CH2N/EVENTOUT 35 -5000 -1050 300 R 50 50 1 1 I
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X PE14/FSMC_D11/TIM1_CH4/EVENTOUT 45 5000 1150 300 L 50 50 1 1 I
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X PD8/FSMC_D13/USART3_TX/EVENTOUT 55 5000 -50 300 L 50 50 1 1 I
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X PC8/TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK/DCMI_D2/EVENTOUT 65 5000 -1850 300 L 50 50 1 1 I
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X VDD 75 450 3000 300 D 50 50 1 1 I
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X PD4/FSMC_NOE/USART2_RTS/EVENTOUT 85 5000 350 300 L 50 50 1 1 I
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X PB8/TIM4_CH3/SDIO_D4/TIM10_CH1/DCMI_D6/ETH_MII_TXD3/I2C1_SCL/CAN1_RX/EVENTOUT 95 -5000 -1850 300 R 50 50 1 1 I
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X PC1/ETH_MDC/_EVENTOUT 16 5000 -1150 300 L 50 50 1 1 I
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X PA3/USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/OTG_HS_ULPI_D0/ETH_MII_COL/EVENTOUT 26 -5000 450 300 R 50 50 1 1 I
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X PB1/TIM3_CH4/TIM8_CH3N/OTG_HS_ULPI_D2/ETH_MII_RXD3/OTG_HS_INTN/TIM1_CH3N/EVENTOUT 36 -5000 -1150 300 R 50 50 1 1 I
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X PE15/FSMC_D12/TIM1_BKIN/EVENTOUT 46 5000 1050 300 L 50 50 1 1 I
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X PD9/FSMC_D14/USART3_RX/EVENTOUT 56 5000 -150 300 L 50 50 1 1 I
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X PC9/I2S_CKIN/MCO2/TIM8_CH4/SDIO_D1/I2C3_SDA/DCMI_D3/TIM3_CH4/EVENTOUT 66 5000 -1950 300 L 50 50 1 1 I
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X PA14/JTCK/SWCLK/EVENTOUT 76 -5000 -650 300 R 50 50 1 1 I
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X PD5/FSMC_NWE/USART2_TX/EVENTOUT 86 5000 250 300 L 50 50 1 1 I
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X PB9/SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/DCMI_D7/I2C1_SDA/CAN1_TX/EVENTOUT 96 -5000 -1950 300 R 50 50 1 1 I
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X PC2/SPI2_MISO/OTG_HS_ULPI_DIR/ETH_MII_TXD2/I2S2ext_SD/EVENTOUT 17 5000 -1250 300 L 50 50 1 1 I
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X VSS 27 0 -3000 300 U 50 50 1 1 I
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X PB2/BOOT1/EVENTOUT 37 -5000 -1250 300 R 50 50 1 1 I
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X PB10/SPI2_SCK/I2S2_CK/I2C2_SCL/USART3_TX/OTG_HS_ULPI_D3/ETH_MII_RX_ER/TIM2_CH3/EVENTOUT 47 -5000 -2050 300 R 50 50 1 1 I
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X PD10/FSMC_D15/USART3_CK/EVENTOUT 57 5000 -250 300 L 50 50 1 1 I
|
|
X PA8/MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF/EVENTOUT 67 -5000 -50 300 R 50 50 1 1 I
|
|
X PA15/JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS/EVENTOUT 77 -5000 -750 300 R 50 50 1 1 I
|
|
X PD6/FSMC_NWAIT/USART2_RX/EVENTOUT 87 5000 150 300 L 50 50 1 1 I
|
|
X PE0/TIM4_ETR/FSMC_NBL0/DCMI_D2/EVENTOUT 97 5000 2550 300 L 50 50 1 1 I
|
|
X PC3/SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT/ETH_MII_TX_CLK/EVENTOUT 18 5000 -1350 300 L 50 50 1 1 I
|
|
X VDD 28 -150 3000 300 D 50 50 1 1 I
|
|
X PE7/FSMC_D4/TIM1_ETR/EVENTOUT 38 5000 1850 300 L 50 50 1 1 I
|
|
X PB11/I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4/ETH_RMII_TX_EN/ETH_MII_TX_EN/TIM2_CH4/EVENTOUT 48 -5000 -2150 300 R 50 50 1 1 I
|
|
X PD11/FSMC_CLE/FSMC_A16/USART3_CTS/EVENTOUT 58 5000 -350 300 L 50 50 1 1 I
|
|
X PA9/USART1_TX/TIM1_CH2/I2C3_SMBA/DCMI_D0/EVENTOUT 68 -5000 -150 300 R 50 50 1 1 I
|
|
X PC10/SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/DCMI_D8/USART3_TX/EVENTOUT 78 5000 -2050 300 L 50 50 1 1 I
|
|
X PD7/USART2_CK/FSMC_NE1/FSMC_NCE2/EVENTOUT 88 5000 50 300 L 50 50 1 1 I
|
|
X PE1/FSMC_NBL1/DCMI_D3/EVENTOUT 98 5000 2450 300 L 50 50 1 1 I
|
|
X VDD 19 -450 3000 300 D 50 50 1 1 I
|
|
X PA4/SPI1_NSS/SPI3_NSS/USART2_CK/DCMI_HSYNC/OTG_HS_SOF/I2S3_WS/EVENTOUT 29 -5000 350 300 R 50 50 1 1 I
|
|
X PE8/FSMC_D5/TIM1_CH1N/EVENTOUT 39 5000 1750 300 L 50 50 1 1 I
|
|
X VCAP_1 49 900 -3000 300 U 50 50 1 1 I
|
|
X PD12/FSMC_ALE/FSMC_A17/TIM4_CH1/USART3_RTS/EVENTOUT 59 5000 -450 300 L 50 50 1 1 I
|
|
X PA10/USART1_RX/TIM1_CH3/OTG_FS_ID/DCMI_D1/EVENTOUT 69 -5000 -250 300 R 50 50 1 1 I
|
|
X PC11/UART4_RX/SPI3_MISO/SDIO_D3/DCMI_D4/USART3_RX/I2S3ext_SD/EVENTOUT 79 5000 -2150 300 L 50 50 1 1 I
|
|
X PB3/JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK/EVENTOUT 89 -5000 -1350 300 R 50 50 1 1 I
|
|
X VSS 99 400 -3000 300 U 50 50 1 1 I
|
|
X VDD 100 750 3000 300 D 50 50 1 1 I
|
|
ENDDRAW
|
|
ENDDEF
|
|
#
|
|
# STM32F407VG
|
|
#
|
|
DEF STM32F407VG U 0 40 Y Y 1 F N
|
|
F0 "U" 0 0 60 H V C CNN
|
|
F1 "STM32F407VG" 0 100 60 H V C CNN
|
|
F2 "TQFP100" 0 -100 60 H V C CNN
|
|
DRAW
|
|
S -4700 -2700 4700 2700 0 1 0 f
|
|
X PE2/TRACECLK/FSMC_A23/ETH_MII_TXD3/EVENTOUT 1 5000 2350 300 L 50 50 1 1 I
|
|
X PE3/TRACED0/FSMC_A19/EVENTOUT 2 5000 2250 300 L 50 50 1 1 I
|
|
X PE4/TRACED1/FSMC_A20/DCMI_D4/EVENTOUT 3 5000 2150 300 L 50 50 1 1 I
|
|
X PE5/TRACED2/FSMC_A21/TIM9_CH1/DCMI_D6/EVENTOUT 4 5000 2050 300 L 50 50 1 1 I
|
|
X PE6/TRACED3_/_FSMC_A22/TIM9_CH2/DCMI_D7/EVENTOUT 5 5000 1950 300 L 50 50 1 1 I
|
|
X VBAT 6 1250 3000 300 D 50 50 1 1 I
|
|
X PC13/EVENTOUT 7 5000 -2350 300 L 50 50 1 1 I
|
|
X PC14/OSC32_IN/EVENTOUT 8 5000 -2450 300 L 50 50 1 1 I
|
|
X PC15/OSC32_OUT/EVENTOUT 9 5000 -2550 300 L 50 50 1 1 I
|
|
X VSS 10 -200 -3000 300 U 50 50 1 1 I
|
|
X VSSA 20 -400 -3000 300 U 50 50 1 1 I
|
|
X PA5/SPI1_SCK/OTG_HS_ULPI_CK/TIM2_CH1_ETR/TIM8_CHIN/EVENTOUT 30 -5000 250 300 R 50 50 1 1 I
|
|
X PE9/FSMC_D6/TIM1_CH1/EVENTOUT 40 5000 1650 300 L 50 50 1 1 I
|
|
X VDD 50 150 3000 300 D 50 50 1 1 I
|
|
X PD13/FSMC_A18/TIM4_CH2/EVENTOUT 60 5000 -550 300 L 50 50 1 1 I
|
|
X PA11/USART1_CTS/CAN1_RX/TIM1_CH4_/OTG_FS_DM/EVENTOUT 70 -5000 -350 300 R 50 50 1 1 I
|
|
X PC12/UART5_TX/SDIO_CK/DCMI_D9/SPI3_MOSI/I2S3_SD/USART3_CK/EVENTOUT 80 5000 -2250 300 L 50 50 1 1 I
|
|
X PB4/NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD/EVENTOUT 90 -5000 -1450 300 R 50 50 1 1 I
|
|
X VDD 11 -750 3000 300 D 50 50 1 1 I
|
|
X VREF+ 21 -2250 3000 300 D 50 50 1 1 I
|
|
X PA6/SPI1_MISO/TIM8_BKIN/TIM13_CH1/DCMI_PIXCLK/TIM3_CH1/TIM1_BKIN/EVENTOUT 31 -5000 150 300 R 50 50 1 1 I
|
|
X PE10/FSMC_D7/TIM1_CH2N/EVENTOUT 41 5000 1550 300 L 50 50 1 1 I
|
|
X PB12/SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN/CAN2_RX/OTG_HS_ULPI_D5/ETH_RMII_TXD0/ETH_MII_TXD0/OTG_HS_ID/EVENTOUT 51 -5000 -2250 300 R 50 50 1 1 I
|
|
X PD14/FSMC_D0/TIM4_CH3/EVENTOUT/_EVENTOUT 61 5000 -650 300 L 50 50 1 1 I
|
|
X PA12/USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP/EVENTOUT 71 -5000 -450 300 R 50 50 1 1 I
|
|
X PD0/FSMC_D2/CAN1_RX/EVENTOUT 81 5000 750 300 L 50 50 1 1 I
|
|
X PB5/I2C1_SMBA/CAN2_RX/OTG_HS_ULPI_D7/ETH_PPS_OUT/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/DCMI_D10/I2S3_SD/EVENTOUT 91 -5000 -1550 300 R 50 50 1 1 I
|
|
X PH0/OSC_IN/EVENTOUT 12 -5000 2150 300 R 50 50 1 1 I
|
|
X VDDA 22 -1750 3000 300 D 50 50 1 1 I
|
|
X PA7/SPI1_MOSI/TIM8_CH1N/TIM14_CH1/TIM3_CH2/ETH_MII_RX_DV/TIM1_CH1N/RMII_CRS_DV/EVENTOUT 32 -5000 50 300 R 50 50 1 1 I
|
|
X PE11/FSMC_D8/TIM1_CH2/EVENTOUT 42 5000 1450 300 L 50 50 1 1 I
|
|
X PB13/SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N/CAN2_TX/OTG_HS_ULPI_D6/ETH_RMII_TXD1/ETH_MII_TXD1/EVENTOUT 52 -5000 -2350 300 R 50 50 1 1 I
|
|
X PD15/FSMC_D1/TIM4_CH4/EVENTOUT 62 5000 -750 300 L 50 50 1 1 I
|
|
X PA13/JTMS/SWDIO/EVENTOUT 72 -5000 -550 300 R 50 50 1 1 I
|
|
X PD1/FSMC_D3/CAN1_TX/EVENTOUT 82 5000 650 300 L 50 50 1 1 I
|
|
X PB6/I2C1_SCL/TIM4_CH1/CAN2_TX/DCMI_D5/USART1_TX/EVENTOUT 92 -5000 -1650 300 R 50 50 1 1 I
|
|
X PH1/OSC_OUT/EVENTOUT 13 -5000 1550 300 R 50 50 1 1 I
|
|
X PA0/WKUP/USART2_CTS/UART4_TX/ETH_MII_CRS_/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR/EVENTOUT 23 -5000 750 300 R 50 50 1 1 I
|
|
X PC4/ETH_RMII_RX_D0/ETH_MII_RX_D0/EVENTOUT 33 5000 -1450 300 L 50 50 1 1 I
|
|
X PE12/FSMC_D9/TIM1_CH3N/EVENTOUT 43 5000 1350 300 L 50 50 1 1 I
|
|
X PB14/SPI2_MISO/TIM1_CH2N/TIM12_CH1/OTG_HS_DM/USART3_RTS/TIM8_CH2N/I2S2ext_SD/EVENTOUT 53 -5000 -2450 300 R 50 50 1 1 I
|
|
X PC6/I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/DCMI_D0/TIM3_CH1/EVENTOUT 63 5000 -1650 300 L 50 50 1 1 I
|
|
X VCAP_2 73 1400 -3000 300 U 50 50 1 1 I
|
|
X PD2/TIM3_ETR/UART5_RX/SDIO_CMD/DCMI_D11/EVENTOUT 83 5000 550 300 L 50 50 1 1 I
|
|
X PB7/I2C1_SDA/FSMC_NL/DCMI_VSYNC/USART1_RX/TIM4_CH2/EVENTOUT 93 -5000 -1750 300 R 50 50 1 1 I
|
|
X NRST 14 -5000 2350 300 R 50 50 1 1 I
|
|
X PA1/USART2_RTS/UART4_RX/ETH_RMII_REF_CLK/ETH_MII_RX_CLK/TIM5_CH2/TIMM2_CH2/EVENTOUT 24 -5000 650 300 R 50 50 1 1 I
|
|
X PC5/ETH_RMII_RX_D1/ETH_MII_RX_D1/EVENTOUT 34 5000 -1550 300 L 50 50 1 1 I
|
|
X PE13/FSMC_D10/TIM1_CH3/EVENTOUT 44 5000 1250 300 L 50 50 1 1 I
|
|
X PB15/SPI2_MOSI/I2S2_SD/TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP/EVENTOUT 54 -5000 -2550 300 R 50 50 1 1 I
|
|
X PC7/I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/DCMI_D1/TIM3_CH2/EVENTOUT 64 5000 -1750 300 L 50 50 1 1 I
|
|
X VSS 74 200 -3000 300 U 50 50 1 1 I
|
|
X PD3/FSMC_CLK/USART2_CTS/EVENTOUT 84 5000 450 300 L 50 50 1 1 I
|
|
X BOOT0 94 -5000 2550 300 R 50 50 1 1 I
|
|
X PC0/OTG_HS_ULPI_STP/EVENTOUT 15 5000 -1050 300 L 50 50 1 1 I
|
|
X PA2/USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3/ETH_MDIO/EVENTOUT 25 -5000 550 300 R 50 50 1 1 I
|
|
X PB0/TIM3_CH3/TIM8_CH2N/OTG_HS_ULPI_D1/ETH_MII_RXD2/TIM1_CH2N/EVENTOUT 35 -5000 -1050 300 R 50 50 1 1 I
|
|
X PE14/FSMC_D11/TIM1_CH4/EVENTOUT 45 5000 1150 300 L 50 50 1 1 I
|
|
X PD8/FSMC_D13/USART3_TX/EVENTOUT 55 5000 -50 300 L 50 50 1 1 I
|
|
X PC8/TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK/DCMI_D2/EVENTOUT 65 5000 -1850 300 L 50 50 1 1 I
|
|
X VDD 75 450 3000 300 D 50 50 1 1 I
|
|
X PD4/FSMC_NOE/USART2_RTS/EVENTOUT 85 5000 350 300 L 50 50 1 1 I
|
|
X PB8/TIM4_CH3/SDIO_D4/TIM10_CH1/DCMI_D6/ETH_MII_TXD3/I2C1_SCL/CAN1_RX/EVENTOUT 95 -5000 -1850 300 R 50 50 1 1 I
|
|
X PC1/ETH_MDC/_EVENTOUT 16 5000 -1150 300 L 50 50 1 1 I
|
|
X PA3/USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/OTG_HS_ULPI_D0/ETH_MII_COL/EVENTOUT 26 -5000 450 300 R 50 50 1 1 I
|
|
X PB1/TIM3_CH4/TIM8_CH3N/OTG_HS_ULPI_D2/ETH_MII_RXD3/OTG_HS_INTN/TIM1_CH3N/EVENTOUT 36 -5000 -1150 300 R 50 50 1 1 I
|
|
X PE15/FSMC_D12/TIM1_BKIN/EVENTOUT 46 5000 1050 300 L 50 50 1 1 I
|
|
X PD9/FSMC_D14/USART3_RX/EVENTOUT 56 5000 -150 300 L 50 50 1 1 I
|
|
X PC9/I2S_CKIN/MCO2/TIM8_CH4/SDIO_D1/I2C3_SDA/DCMI_D3/TIM3_CH4/EVENTOUT 66 5000 -1950 300 L 50 50 1 1 I
|
|
X PA14/JTCK/SWCLK/EVENTOUT 76 -5000 -650 300 R 50 50 1 1 I
|
|
X PD5/FSMC_NWE/USART2_TX/EVENTOUT 86 5000 250 300 L 50 50 1 1 I
|
|
X PB9/SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/DCMI_D7/I2C1_SDA/CAN1_TX/EVENTOUT 96 -5000 -1950 300 R 50 50 1 1 I
|
|
X PC2/SPI2_MISO/OTG_HS_ULPI_DIR/ETH_MII_TXD2/I2S2ext_SD/EVENTOUT 17 5000 -1250 300 L 50 50 1 1 I
|
|
X VSS 27 0 -3000 300 U 50 50 1 1 I
|
|
X PB2/BOOT1/EVENTOUT 37 -5000 -1250 300 R 50 50 1 1 I
|
|
X PB10/SPI2_SCK/I2S2_CK/I2C2_SCL/USART3_TX/OTG_HS_ULPI_D3/ETH_MII_RX_ER/TIM2_CH3/EVENTOUT 47 -5000 -2050 300 R 50 50 1 1 I
|
|
X PD10/FSMC_D15/USART3_CK/EVENTOUT 57 5000 -250 300 L 50 50 1 1 I
|
|
X PA8/MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF/EVENTOUT 67 -5000 -50 300 R 50 50 1 1 I
|
|
X PA15/JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS/EVENTOUT 77 -5000 -750 300 R 50 50 1 1 I
|
|
X PD6/FSMC_NWAIT/USART2_RX/EVENTOUT 87 5000 150 300 L 50 50 1 1 I
|
|
X PE0/TIM4_ETR/FSMC_NBL0/DCMI_D2/EVENTOUT 97 5000 2550 300 L 50 50 1 1 I
|
|
X PC3/SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT/ETH_MII_TX_CLK/EVENTOUT 18 5000 -1350 300 L 50 50 1 1 I
|
|
X VDD 28 -150 3000 300 D 50 50 1 1 I
|
|
X PE7/FSMC_D4/TIM1_ETR/EVENTOUT 38 5000 1850 300 L 50 50 1 1 I
|
|
X PB11/I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4/ETH_RMII_TX_EN/ETH_MII_TX_EN/TIM2_CH4/EVENTOUT 48 -5000 -2150 300 R 50 50 1 1 I
|
|
X PD11/FSMC_CLE/FSMC_A16/USART3_CTS/EVENTOUT 58 5000 -350 300 L 50 50 1 1 I
|
|
X PA9/USART1_TX/TIM1_CH2/I2C3_SMBA/DCMI_D0/EVENTOUT 68 -5000 -150 300 R 50 50 1 1 I
|
|
X PC10/SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/DCMI_D8/USART3_TX/EVENTOUT 78 5000 -2050 300 L 50 50 1 1 I
|
|
X PD7/USART2_CK/FSMC_NE1/FSMC_NCE2/EVENTOUT 88 5000 50 300 L 50 50 1 1 I
|
|
X PE1/FSMC_NBL1/DCMI_D3/EVENTOUT 98 5000 2450 300 L 50 50 1 1 I
|
|
X VDD 19 -450 3000 300 D 50 50 1 1 I
|
|
X PA4/SPI1_NSS/SPI3_NSS/USART2_CK/DCMI_HSYNC/OTG_HS_SOF/I2S3_WS/EVENTOUT 29 -5000 350 300 R 50 50 1 1 I
|
|
X PE8/FSMC_D5/TIM1_CH1N/EVENTOUT 39 5000 1750 300 L 50 50 1 1 I
|
|
X VCAP_1 49 900 -3000 300 U 50 50 1 1 I
|
|
X PD12/FSMC_ALE/FSMC_A17/TIM4_CH1/USART3_RTS/EVENTOUT 59 5000 -450 300 L 50 50 1 1 I
|
|
X PA10/USART1_RX/TIM1_CH3/OTG_FS_ID/DCMI_D1/EVENTOUT 69 -5000 -250 300 R 50 50 1 1 I
|
|
X PC11/UART4_RX/SPI3_MISO/SDIO_D3/DCMI_D4/USART3_RX/I2S3ext_SD/EVENTOUT 79 5000 -2150 300 L 50 50 1 1 I
|
|
X PB3/JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK/EVENTOUT 89 -5000 -1350 300 R 50 50 1 1 I
|
|
X VSS 99 400 -3000 300 U 50 50 1 1 I
|
|
X VDD 100 750 3000 300 D 50 50 1 1 I
|
|
ENDDRAW
|
|
ENDDEF
|
|
#
|
|
# STM32F415VG
|
|
#
|
|
DEF STM32F415VG U 0 40 Y Y 1 F N
|
|
F0 "U" 0 0 60 H V C CNN
|
|
F1 "STM32F415VG" 0 100 60 H V C CNN
|
|
F2 "TQFP100" 0 -100 60 H V C CNN
|
|
DRAW
|
|
S -4700 -2700 4700 2700 0 1 0 f
|
|
X PE2/TRACECLK/FSMC_A23/EVENTOUT 1 5000 2350 300 L 50 50 1 1 I
|
|
X PE3/TRACED0/FSMC_A19/EVENTOUT 2 5000 2250 300 L 50 50 1 1 I
|
|
X PE4/TRACED1/FSMC_A20/EVENTOUT 3 5000 2150 300 L 50 50 1 1 I
|
|
X PE5/TRACED2/FSMC_A21/TIM9_CH1/EVENTOUT 4 5000 2050 300 L 50 50 1 1 I
|
|
X PE6/TRACED3_/_FSMC_A22/TIM9_CH2/EVENTOUT 5 5000 1950 300 L 50 50 1 1 I
|
|
X VBAT 6 1250 3000 300 D 50 50 1 1 I
|
|
X PC13/EVENTOUT 7 5000 -2350 300 L 50 50 1 1 I
|
|
X PC14/OSC32_IN/EVENTOUT 8 5000 -2450 300 L 50 50 1 1 I
|
|
X PC15/OSC32_OUT/EVENTOUT 9 5000 -2550 300 L 50 50 1 1 I
|
|
X VSS 10 -200 -3000 300 U 50 50 1 1 I
|
|
X VSSA 20 -400 -3000 300 U 50 50 1 1 I
|
|
X PA5/SPI1_SCK/OTG_HS_ULPI_CK/TIM2_CH1_ETR/TIM8_CHIN/EVENTOUT 30 -5000 250 300 R 50 50 1 1 I
|
|
X PE9/FSMC_D6/TIM1_CH1/EVENTOUT 40 5000 1650 300 L 50 50 1 1 I
|
|
X VDD 50 150 3000 300 D 50 50 1 1 I
|
|
X PD13/FSMC_A18/TIM4_CH2/EVENTOUT 60 5000 -550 300 L 50 50 1 1 I
|
|
X PA11/USART1_CTS/CAN1_RX/TIM1_CH4_/OTG_FS_DM/EVENTOUT 70 -5000 -350 300 R 50 50 1 1 I
|
|
X PC12/UART5_TX/SDIO_CK/SPI3_MOSI/I2S3_SD/USART3_CK/EVENTOUT 80 5000 -2250 300 L 50 50 1 1 I
|
|
X PB4/NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD/EVENTOUT 90 -5000 -1450 300 R 50 50 1 1 I
|
|
X VDD 11 -750 3000 300 D 50 50 1 1 I
|
|
X VREF+ 21 -2250 3000 300 D 50 50 1 1 I
|
|
X PA6/SPI1_MISO/TIM8_BKIN/TIM13_CH1/TIM3_CH1/TIM1_BKIN/EVENTOUT 31 -5000 150 300 R 50 50 1 1 I
|
|
X PE10/FSMC_D7/TIM1_CH2N/EVENTOUT 41 5000 1550 300 L 50 50 1 1 I
|
|
X PB12/SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN/CAN2_RX/OTG_HS_ULPI_D5/OTG_HS_ID/EVENTOUT 51 -5000 -2250 300 R 50 50 1 1 I
|
|
X PD14/FSMC_D0/TIM4_CH3/EVENTOUT/_EVENTOUT 61 5000 -650 300 L 50 50 1 1 I
|
|
X PA12/USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP/EVENTOUT 71 -5000 -450 300 R 50 50 1 1 I
|
|
X PD0/FSMC_D2/CAN1_RX/EVENTOUT 81 5000 750 300 L 50 50 1 1 I
|
|
X PB5/I2C1_SMBA/CAN2_RX/OTG_HS_ULPI_D7/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/I2S3_SD/EVENTOUT 91 -5000 -1550 300 R 50 50 1 1 I
|
|
X PH0/OSC_IN/EVENTOUT 12 -5000 2150 300 R 50 50 1 1 I
|
|
X VDDA 22 -1750 3000 300 D 50 50 1 1 I
|
|
X PA7/SPI1_MOSI/TIM8_CH1N/TIM14_CH1/TIM3_CH2/TIM1_CH1N/EVENTOUT 32 -5000 50 300 R 50 50 1 1 I
|
|
X PE11/FSMC_D8/TIM1_CH2/EVENTOUT 42 5000 1450 300 L 50 50 1 1 I
|
|
X PB13/SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N/CAN2_TX/OTG_HS_ULPI_D6/EVENTOUT 52 -5000 -2350 300 R 50 50 1 1 I
|
|
X PD15/FSMC_D1/TIM4_CH4/EVENTOUT 62 5000 -750 300 L 50 50 1 1 I
|
|
X PA13/JTMS/SWDIO/EVENTOUT 72 -5000 -550 300 R 50 50 1 1 I
|
|
X PD1/FSMC_D3/CAN1_TX/EVENTOUT 82 5000 650 300 L 50 50 1 1 I
|
|
X PB6/I2C1_SCL/TIM4_CH1/CAN2_TX/USART1_TX/EVENTOUT 92 -5000 -1650 300 R 50 50 1 1 I
|
|
X PH1/OSC_OUT/EVENTOUT 13 -5000 1550 300 R 50 50 1 1 I
|
|
X PA0/WKUP/USART2_CTS/UART4_TX/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR/EVENTOUT 23 -5000 750 300 R 50 50 1 1 I
|
|
X PC4/EVENTOUT 33 5000 -1450 300 L 50 50 1 1 I
|
|
X PE12/FSMC_D9/TIM1_CH3N/EVENTOUT 43 5000 1350 300 L 50 50 1 1 I
|
|
X PB14/SPI2_MISO/TIM1_CH2N/TIM12_CH1/OTG_HS_DM/USART3_RTS/TIM8_CH2N/I2S2ext_SD/EVENTOUT 53 -5000 -2450 300 R 50 50 1 1 I
|
|
X PC6/I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/TIM3_CH1/EVENTOUT 63 5000 -1650 300 L 50 50 1 1 I
|
|
X VCAP_2 73 1400 -3000 300 U 50 50 1 1 I
|
|
X PD2/TIM3_ETR/UART5_RX/SDIO_CMD/EVENTOUT 83 5000 550 300 L 50 50 1 1 I
|
|
X PB7/I2C1_SDA/FSMC_NL/USART1_RX/TIM4_CH2/EVENTOUT 93 -5000 -1750 300 R 50 50 1 1 I
|
|
X NRST 14 -5000 2350 300 R 50 50 1 1 I
|
|
X PA1/USART2_RTS/UART4_RX/TIM5_CH2/TIMM2_CH2/EVENTOUT 24 -5000 650 300 R 50 50 1 1 I
|
|
X PC5/EVENTOUT 34 5000 -1550 300 L 50 50 1 1 I
|
|
X PE13/FSMC_D10/TIM1_CH3/EVENTOUT 44 5000 1250 300 L 50 50 1 1 I
|
|
X PB15/SPI2_MOSI/I2S2_SD/TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP/EVENTOUT 54 -5000 -2550 300 R 50 50 1 1 I
|
|
X PC7/I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/TIM3_CH2/EVENTOUT 64 5000 -1750 300 L 50 50 1 1 I
|
|
X VSS 74 200 -3000 300 U 50 50 1 1 I
|
|
X PD3/FSMC_CLK/USART2_CTS/EVENTOUT 84 5000 450 300 L 50 50 1 1 I
|
|
X BOOT0 94 -5000 2550 300 R 50 50 1 1 I
|
|
X PC0/OTG_HS_ULPI_STP/EVENTOUT 15 5000 -1050 300 L 50 50 1 1 I
|
|
X PA2/USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3/EVENTOUT 25 -5000 550 300 R 50 50 1 1 I
|
|
X PB0/TIM3_CH3/TIM8_CH2N/OTG_HS_ULPI_D1/TIM1_CH2N/EVENTOUT 35 -5000 -1050 300 R 50 50 1 1 I
|
|
X PE14/FSMC_D11/TIM1_CH4/EVENTOUT 45 5000 1150 300 L 50 50 1 1 I
|
|
X PD8/FSMC_D13/USART3_TX/EVENTOUT 55 5000 -50 300 L 50 50 1 1 I
|
|
X PC8/TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK/EVENTOUT 65 5000 -1850 300 L 50 50 1 1 I
|
|
X VDD 75 450 3000 300 D 50 50 1 1 I
|
|
X PD4/FSMC_NOE/USART2_RTS/EVENTOUT 85 5000 350 300 L 50 50 1 1 I
|
|
X PB8/TIM4_CH3/SDIO_D4/TIM10_CH1/I2C1_SCL/CAN1_RX/EVENTOUT 95 -5000 -1850 300 R 50 50 1 1 I
|
|
X PC1/_EVENTOUT 16 5000 -1150 300 L 50 50 1 1 I
|
|
X PA3/USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/OTG_HS_ULPI_D0/EVENTOUT 26 -5000 450 300 R 50 50 1 1 I
|
|
X PB1/TIM3_CH4/TIM8_CH3N/OTG_HS_ULPI_D2/OTG_HS_INTN/TIM1_CH3N/EVENTOUT 36 -5000 -1150 300 R 50 50 1 1 I
|
|
X PE15/FSMC_D12/TIM1_BKIN/EVENTOUT 46 5000 1050 300 L 50 50 1 1 I
|
|
X PD9/FSMC_D14/USART3_RX/EVENTOUT 56 5000 -150 300 L 50 50 1 1 I
|
|
X PC9/I2S_CKIN/MCO2/TIM8_CH4/SDIO_D1/I2C3_SDA/TIM3_CH4/EVENTOUT 66 5000 -1950 300 L 50 50 1 1 I
|
|
X PA14/JTCK/SWCLK/EVENTOUT 76 -5000 -650 300 R 50 50 1 1 I
|
|
X PD5/FSMC_NWE/USART2_TX/EVENTOUT 86 5000 250 300 L 50 50 1 1 I
|
|
X PB9/SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/I2C1_SDA/CAN1_TX/EVENTOUT 96 -5000 -1950 300 R 50 50 1 1 I
|
|
X PC2/SPI2_MISO/OTG_HS_ULPI_DIR/I2S2ext_SD/EVENTOUT 17 5000 -1250 300 L 50 50 1 1 I
|
|
X VSS 27 0 -3000 300 U 50 50 1 1 I
|
|
X PB2/BOOT1/EVENTOUT 37 -5000 -1250 300 R 50 50 1 1 I
|
|
X PB10/SPI2_SCK/I2S2_CK/I2C2_SCL/USART3_TX/OTG_HS_ULPI_D3/TIM2_CH3/EVENTOUT 47 -5000 -2050 300 R 50 50 1 1 I
|
|
X PD10/FSMC_D15/USART3_CK/EVENTOUT 57 5000 -250 300 L 50 50 1 1 I
|
|
X PA8/MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF/EVENTOUT 67 -5000 -50 300 R 50 50 1 1 I
|
|
X PA15/JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS/EVENTOUT 77 -5000 -750 300 R 50 50 1 1 I
|
|
X PD6/FSMC_NWAIT/USART2_RX/EVENTOUT 87 5000 150 300 L 50 50 1 1 I
|
|
X PE0/TIM4_ETR/FSMC_NBL0/EVENTOUT 97 5000 2550 300 L 50 50 1 1 I
|
|
X PC3/SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT/EVENTOUT 18 5000 -1350 300 L 50 50 1 1 I
|
|
X VDD 28 -150 3000 300 D 50 50 1 1 I
|
|
X PE7/FSMC_D4/TIM1_ETR/EVENTOUT 38 5000 1850 300 L 50 50 1 1 I
|
|
X PB11/I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4/TIM2_CH4/EVENTOUT 48 -5000 -2150 300 R 50 50 1 1 I
|
|
X PD11/FSMC_CLE/FSMC_A16/USART3_CTS/EVENTOUT 58 5000 -350 300 L 50 50 1 1 I
|
|
X PA9/USART1_TX/TIM1_CH2/I2C3_SMBA/EVENTOUT 68 -5000 -150 300 R 50 50 1 1 I
|
|
X PC10/SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/USART3_TX/EVENTOUT 78 5000 -2050 300 L 50 50 1 1 I
|
|
X PD7/USART2_CK/FSMC_NE1/FSMC_NCE2/EVENTOUT 88 5000 50 300 L 50 50 1 1 I
|
|
X PE1/FSMC_NBL1/EVENTOUT 98 5000 2450 300 L 50 50 1 1 I
|
|
X VDD 19 -450 3000 300 D 50 50 1 1 I
|
|
X PA4/SPI1_NSS/SPI3_NSS/USART2_CK/OTG_HS_SOF/I2S3_WS/EVENTOUT 29 -5000 350 300 R 50 50 1 1 I
|
|
X PE8/FSMC_D5/TIM1_CH1N/EVENTOUT 39 5000 1750 300 L 50 50 1 1 I
|
|
X VCAP_1 49 900 -3000 300 U 50 50 1 1 I
|
|
X PD12/FSMC_ALE/FSMC_A17/TIM4_CH1/USART3_RTS/EVENTOUT 59 5000 -450 300 L 50 50 1 1 I
|
|
X PA10/USART1_RX/TIM1_CH3/OTG_FS_ID/EVENTOUT 69 -5000 -250 300 R 50 50 1 1 I
|
|
X PC11/UART4_RX/SPI3_MISO/SDIO_D3/USART3_RX/I2S3ext_SD/EVENTOUT 79 5000 -2150 300 L 50 50 1 1 I
|
|
X PB3/JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK/EVENTOUT 89 -5000 -1350 300 R 50 50 1 1 I
|
|
X VSS 99 400 -3000 300 U 50 50 1 1 I
|
|
X VDD 100 750 3000 300 D 50 50 1 1 I
|
|
ENDDRAW
|
|
ENDDEF
|
|
#
|
|
# STM32F417VE
|
|
#
|
|
DEF STM32F417VE U 0 40 Y Y 1 F N
|
|
F0 "U" 0 0 60 H V C CNN
|
|
F1 "STM32F417VE" 0 100 60 H V C CNN
|
|
F2 "TQFP100" 0 -100 60 H V C CNN
|
|
DRAW
|
|
S -4700 -2700 4700 2700 0 1 0 f
|
|
X PE2/TRACECLK/FSMC_A23/ETH_MII_TXD3/EVENTOUT 1 5000 2350 300 L 50 50 1 1 I
|
|
X PE3/TRACED0/FSMC_A19/EVENTOUT 2 5000 2250 300 L 50 50 1 1 I
|
|
X PE4/TRACED1/FSMC_A20/DCMI_D4/EVENTOUT 3 5000 2150 300 L 50 50 1 1 I
|
|
X PE5/TRACED2/FSMC_A21/TIM9_CH1/DCMI_D6/EVENTOUT 4 5000 2050 300 L 50 50 1 1 I
|
|
X PE6/TRACED3_/_FSMC_A22/TIM9_CH2/DCMI_D7/EVENTOUT 5 5000 1950 300 L 50 50 1 1 I
|
|
X VBAT 6 1250 3000 300 D 50 50 1 1 I
|
|
X PC13/EVENTOUT 7 5000 -2350 300 L 50 50 1 1 I
|
|
X PC14/OSC32_IN/EVENTOUT 8 5000 -2450 300 L 50 50 1 1 I
|
|
X PC15/OSC32_OUT/EVENTOUT 9 5000 -2550 300 L 50 50 1 1 I
|
|
X VSS 10 -200 -3000 300 U 50 50 1 1 I
|
|
X VSSA 20 -400 -3000 300 U 50 50 1 1 I
|
|
X PA5/SPI1_SCK/OTG_HS_ULPI_CK/TIM2_CH1_ETR/TIM8_CHIN/EVENTOUT 30 -5000 250 300 R 50 50 1 1 I
|
|
X PE9/FSMC_D6/TIM1_CH1/EVENTOUT 40 5000 1650 300 L 50 50 1 1 I
|
|
X VDD 50 150 3000 300 D 50 50 1 1 I
|
|
X PD13/FSMC_A18/TIM4_CH2/EVENTOUT 60 5000 -550 300 L 50 50 1 1 I
|
|
X PA11/USART1_CTS/CAN1_RX/TIM1_CH4_/OTG_FS_DM/EVENTOUT 70 -5000 -350 300 R 50 50 1 1 I
|
|
X PC12/UART5_TX/SDIO_CK/DCMI_D9/SPI3_MOSI/I2S3_SD/USART3_CK/EVENTOUT 80 5000 -2250 300 L 50 50 1 1 I
|
|
X PB4/NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD/EVENTOUT 90 -5000 -1450 300 R 50 50 1 1 I
|
|
X VDD 11 -750 3000 300 D 50 50 1 1 I
|
|
X VREF+ 21 -2250 3000 300 D 50 50 1 1 I
|
|
X PA6/SPI1_MISO/TIM8_BKIN/TIM13_CH1/DCMI_PIXCLK/TIM3_CH1/TIM1_BKIN/EVENTOUT 31 -5000 150 300 R 50 50 1 1 I
|
|
X PE10/FSMC_D7/TIM1_CH2N/EVENTOUT 41 5000 1550 300 L 50 50 1 1 I
|
|
X PB12/SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN/CAN2_RX/OTG_HS_ULPI_D5/ETH_RMII_TXD0/ETH_MII_TXD0/OTG_HS_ID/EVENTOUT 51 -5000 -2250 300 R 50 50 1 1 I
|
|
X PD14/FSMC_D0/TIM4_CH3/EVENTOUT/_EVENTOUT 61 5000 -650 300 L 50 50 1 1 I
|
|
X PA12/USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP/EVENTOUT 71 -5000 -450 300 R 50 50 1 1 I
|
|
X PD0/FSMC_D2/CAN1_RX/EVENTOUT 81 5000 750 300 L 50 50 1 1 I
|
|
X PB5/I2C1_SMBA/CAN2_RX/OTG_HS_ULPI_D7/ETH_PPS_OUT/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/DCMI_D10/I2S3_SD/EVENTOUT 91 -5000 -1550 300 R 50 50 1 1 I
|
|
X PH0/OSC_IN/EVENTOUT 12 -5000 2150 300 R 50 50 1 1 I
|
|
X VDDA 22 -1750 3000 300 D 50 50 1 1 I
|
|
X PA7/SPI1_MOSI/TIM8_CH1N/TIM14_CH1/TIM3_CH2/ETH_MII_RX_DV/TIM1_CH1N/RMII_CRS_DV/EVENTOUT 32 -5000 50 300 R 50 50 1 1 I
|
|
X PE11/FSMC_D8/TIM1_CH2/EVENTOUT 42 5000 1450 300 L 50 50 1 1 I
|
|
X PB13/SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N/CAN2_TX/OTG_HS_ULPI_D6/ETH_RMII_TXD1/ETH_MII_TXD1/EVENTOUT 52 -5000 -2350 300 R 50 50 1 1 I
|
|
X PD15/FSMC_D1/TIM4_CH4/EVENTOUT 62 5000 -750 300 L 50 50 1 1 I
|
|
X PA13/JTMS/SWDIO/EVENTOUT 72 -5000 -550 300 R 50 50 1 1 I
|
|
X PD1/FSMC_D3/CAN1_TX/EVENTOUT 82 5000 650 300 L 50 50 1 1 I
|
|
X PB6/I2C1_SCL/TIM4_CH1/CAN2_TX/DCMI_D5/USART1_TX/EVENTOUT 92 -5000 -1650 300 R 50 50 1 1 I
|
|
X PH1/OSC_OUT/EVENTOUT 13 -5000 1550 300 R 50 50 1 1 I
|
|
X PA0/WKUP/USART2_CTS/UART4_TX/ETH_MII_CRS_/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR/EVENTOUT 23 -5000 750 300 R 50 50 1 1 I
|
|
X PC4/ETH_RMII_RX_D0/ETH_MII_RX_D0/EVENTOUT 33 5000 -1450 300 L 50 50 1 1 I
|
|
X PE12/FSMC_D9/TIM1_CH3N/EVENTOUT 43 5000 1350 300 L 50 50 1 1 I
|
|
X PB14/SPI2_MISO/TIM1_CH2N/TIM12_CH1/OTG_HS_DM/USART3_RTS/TIM8_CH2N/I2S2ext_SD/EVENTOUT 53 -5000 -2450 300 R 50 50 1 1 I
|
|
X PC6/I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/DCMI_D0/TIM3_CH1/EVENTOUT 63 5000 -1650 300 L 50 50 1 1 I
|
|
X VCAP_2 73 1400 -3000 300 U 50 50 1 1 I
|
|
X PD2/TIM3_ETR/UART5_RX/SDIO_CMD/DCMI_D11/EVENTOUT 83 5000 550 300 L 50 50 1 1 I
|
|
X PB7/I2C1_SDA/FSMC_NL/DCMI_VSYNC/USART1_RX/TIM4_CH2/EVENTOUT 93 -5000 -1750 300 R 50 50 1 1 I
|
|
X NRST 14 -5000 2350 300 R 50 50 1 1 I
|
|
X PA1/USART2_RTS/UART4_RX/ETH_RMII_REF_CLK/ETH_MII_RX_CLK/TIM5_CH2/TIMM2_CH2/EVENTOUT 24 -5000 650 300 R 50 50 1 1 I
|
|
X PC5/ETH_RMII_RX_D1/ETH_MII_RX_D1/EVENTOUT 34 5000 -1550 300 L 50 50 1 1 I
|
|
X PE13/FSMC_D10/TIM1_CH3/EVENTOUT 44 5000 1250 300 L 50 50 1 1 I
|
|
X PB15/SPI2_MOSI/I2S2_SD/TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP/EVENTOUT 54 -5000 -2550 300 R 50 50 1 1 I
|
|
X PC7/I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/DCMI_D1/TIM3_CH2/EVENTOUT 64 5000 -1750 300 L 50 50 1 1 I
|
|
X VSS 74 200 -3000 300 U 50 50 1 1 I
|
|
X PD3/FSMC_CLK/USART2_CTS/EVENTOUT 84 5000 450 300 L 50 50 1 1 I
|
|
X BOOT0 94 -5000 2550 300 R 50 50 1 1 I
|
|
X PC0/OTG_HS_ULPI_STP/EVENTOUT 15 5000 -1050 300 L 50 50 1 1 I
|
|
X PA2/USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3/ETH_MDIO/EVENTOUT 25 -5000 550 300 R 50 50 1 1 I
|
|
X PB0/TIM3_CH3/TIM8_CH2N/OTG_HS_ULPI_D1/ETH_MII_RXD2/TIM1_CH2N/EVENTOUT 35 -5000 -1050 300 R 50 50 1 1 I
|
|
X PE14/FSMC_D11/TIM1_CH4/EVENTOUT 45 5000 1150 300 L 50 50 1 1 I
|
|
X PD8/FSMC_D13/USART3_TX/EVENTOUT 55 5000 -50 300 L 50 50 1 1 I
|
|
X PC8/TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK/DCMI_D2/EVENTOUT 65 5000 -1850 300 L 50 50 1 1 I
|
|
X VDD 75 450 3000 300 D 50 50 1 1 I
|
|
X PD4/FSMC_NOE/USART2_RTS/EVENTOUT 85 5000 350 300 L 50 50 1 1 I
|
|
X PB8/TIM4_CH3/SDIO_D4/TIM10_CH1/DCMI_D6/ETH_MII_TXD3/I2C1_SCL/CAN1_RX/EVENTOUT 95 -5000 -1850 300 R 50 50 1 1 I
|
|
X PC1/ETH_MDC/_EVENTOUT 16 5000 -1150 300 L 50 50 1 1 I
|
|
X PA3/USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/OTG_HS_ULPI_D0/ETH_MII_COL/EVENTOUT 26 -5000 450 300 R 50 50 1 1 I
|
|
X PB1/TIM3_CH4/TIM8_CH3N/OTG_HS_ULPI_D2/ETH_MII_RXD3/OTG_HS_INTN/TIM1_CH3N/EVENTOUT 36 -5000 -1150 300 R 50 50 1 1 I
|
|
X PE15/FSMC_D12/TIM1_BKIN/EVENTOUT 46 5000 1050 300 L 50 50 1 1 I
|
|
X PD9/FSMC_D14/USART3_RX/EVENTOUT 56 5000 -150 300 L 50 50 1 1 I
|
|
X PC9/I2S_CKIN/MCO2/TIM8_CH4/SDIO_D1/I2C3_SDA/DCMI_D3/TIM3_CH4/EVENTOUT 66 5000 -1950 300 L 50 50 1 1 I
|
|
X PA14/JTCK/SWCLK/EVENTOUT 76 -5000 -650 300 R 50 50 1 1 I
|
|
X PD5/FSMC_NWE/USART2_TX/EVENTOUT 86 5000 250 300 L 50 50 1 1 I
|
|
X PB9/SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/DCMI_D7/I2C1_SDA/CAN1_TX/EVENTOUT 96 -5000 -1950 300 R 50 50 1 1 I
|
|
X PC2/SPI2_MISO/OTG_HS_ULPI_DIR/ETH_MII_TXD2/I2S2ext_SD/EVENTOUT 17 5000 -1250 300 L 50 50 1 1 I
|
|
X VSS 27 0 -3000 300 U 50 50 1 1 I
|
|
X PB2/BOOT1/EVENTOUT 37 -5000 -1250 300 R 50 50 1 1 I
|
|
X PB10/SPI2_SCK/I2S2_CK/I2C2_SCL/USART3_TX/OTG_HS_ULPI_D3/ETH_MII_RX_ER/TIM2_CH3/EVENTOUT 47 -5000 -2050 300 R 50 50 1 1 I
|
|
X PD10/FSMC_D15/USART3_CK/EVENTOUT 57 5000 -250 300 L 50 50 1 1 I
|
|
X PA8/MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF/EVENTOUT 67 -5000 -50 300 R 50 50 1 1 I
|
|
X PA15/JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS/EVENTOUT 77 -5000 -750 300 R 50 50 1 1 I
|
|
X PD6/FSMC_NWAIT/USART2_RX/EVENTOUT 87 5000 150 300 L 50 50 1 1 I
|
|
X PE0/TIM4_ETR/FSMC_NBL0/DCMI_D2/EVENTOUT 97 5000 2550 300 L 50 50 1 1 I
|
|
X PC3/SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT/ETH_MII_TX_CLK/EVENTOUT 18 5000 -1350 300 L 50 50 1 1 I
|
|
X VDD 28 -150 3000 300 D 50 50 1 1 I
|
|
X PE7/FSMC_D4/TIM1_ETR/EVENTOUT 38 5000 1850 300 L 50 50 1 1 I
|
|
X PB11/I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4/ETH_RMII_TX_EN/ETH_MII_TX_EN/TIM2_CH4/EVENTOUT 48 -5000 -2150 300 R 50 50 1 1 I
|
|
X PD11/FSMC_CLE/FSMC_A16/USART3_CTS/EVENTOUT 58 5000 -350 300 L 50 50 1 1 I
|
|
X PA9/USART1_TX/TIM1_CH2/I2C3_SMBA/DCMI_D0/EVENTOUT 68 -5000 -150 300 R 50 50 1 1 I
|
|
X PC10/SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/DCMI_D8/USART3_TX/EVENTOUT 78 5000 -2050 300 L 50 50 1 1 I
|
|
X PD7/USART2_CK/FSMC_NE1/FSMC_NCE2/EVENTOUT 88 5000 50 300 L 50 50 1 1 I
|
|
X PE1/FSMC_NBL1/DCMI_D3/EVENTOUT 98 5000 2450 300 L 50 50 1 1 I
|
|
X VDD 19 -450 3000 300 D 50 50 1 1 I
|
|
X PA4/SPI1_NSS/SPI3_NSS/USART2_CK/DCMI_HSYNC/OTG_HS_SOF/I2S3_WS/EVENTOUT 29 -5000 350 300 R 50 50 1 1 I
|
|
X PE8/FSMC_D5/TIM1_CH1N/EVENTOUT 39 5000 1750 300 L 50 50 1 1 I
|
|
X VCAP_1 49 900 -3000 300 U 50 50 1 1 I
|
|
X PD12/FSMC_ALE/FSMC_A17/TIM4_CH1/USART3_RTS/EVENTOUT 59 5000 -450 300 L 50 50 1 1 I
|
|
X PA10/USART1_RX/TIM1_CH3/OTG_FS_ID/DCMI_D1/EVENTOUT 69 -5000 -250 300 R 50 50 1 1 I
|
|
X PC11/UART4_RX/SPI3_MISO/SDIO_D3/DCMI_D4/USART3_RX/I2S3ext_SD/EVENTOUT 79 5000 -2150 300 L 50 50 1 1 I
|
|
X PB3/JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK/EVENTOUT 89 -5000 -1350 300 R 50 50 1 1 I
|
|
X VSS 99 400 -3000 300 U 50 50 1 1 I
|
|
X VDD 100 750 3000 300 D 50 50 1 1 I
|
|
ENDDRAW
|
|
ENDDEF
|
|
#
|
|
# STM32F417VG
|
|
#
|
|
DEF STM32F417VG U 0 40 Y Y 1 F N
|
|
F0 "U" 0 0 60 H V C CNN
|
|
F1 "STM32F417VG" 0 100 60 H V C CNN
|
|
F2 "TQFP100" 0 -100 60 H V C CNN
|
|
DRAW
|
|
S -4700 -2700 4700 2700 0 1 0 f
|
|
X PE2/TRACECLK/FSMC_A23/ETH_MII_TXD3/EVENTOUT 1 5000 2350 300 L 50 50 1 1 I
|
|
X PE3/TRACED0/FSMC_A19/EVENTOUT 2 5000 2250 300 L 50 50 1 1 I
|
|
X PE4/TRACED1/FSMC_A20/DCMI_D4/EVENTOUT 3 5000 2150 300 L 50 50 1 1 I
|
|
X PE5/TRACED2/FSMC_A21/TIM9_CH1/DCMI_D6/EVENTOUT 4 5000 2050 300 L 50 50 1 1 I
|
|
X PE6/TRACED3_/_FSMC_A22/TIM9_CH2/DCMI_D7/EVENTOUT 5 5000 1950 300 L 50 50 1 1 I
|
|
X VBAT 6 1250 3000 300 D 50 50 1 1 I
|
|
X PC13/EVENTOUT 7 5000 -2350 300 L 50 50 1 1 I
|
|
X PC14/OSC32_IN/EVENTOUT 8 5000 -2450 300 L 50 50 1 1 I
|
|
X PC15/OSC32_OUT/EVENTOUT 9 5000 -2550 300 L 50 50 1 1 I
|
|
X VSS 10 -200 -3000 300 U 50 50 1 1 I
|
|
X VSSA 20 -400 -3000 300 U 50 50 1 1 I
|
|
X PA5/SPI1_SCK/OTG_HS_ULPI_CK/TIM2_CH1_ETR/TIM8_CHIN/EVENTOUT 30 -5000 250 300 R 50 50 1 1 I
|
|
X PE9/FSMC_D6/TIM1_CH1/EVENTOUT 40 5000 1650 300 L 50 50 1 1 I
|
|
X VDD 50 150 3000 300 D 50 50 1 1 I
|
|
X PD13/FSMC_A18/TIM4_CH2/EVENTOUT 60 5000 -550 300 L 50 50 1 1 I
|
|
X PA11/USART1_CTS/CAN1_RX/TIM1_CH4_/OTG_FS_DM/EVENTOUT 70 -5000 -350 300 R 50 50 1 1 I
|
|
X PC12/UART5_TX/SDIO_CK/DCMI_D9/SPI3_MOSI/I2S3_SD/USART3_CK/EVENTOUT 80 5000 -2250 300 L 50 50 1 1 I
|
|
X PB4/NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD/EVENTOUT 90 -5000 -1450 300 R 50 50 1 1 I
|
|
X VDD 11 -750 3000 300 D 50 50 1 1 I
|
|
X VREF+ 21 -2250 3000 300 D 50 50 1 1 I
|
|
X PA6/SPI1_MISO/TIM8_BKIN/TIM13_CH1/DCMI_PIXCLK/TIM3_CH1/TIM1_BKIN/EVENTOUT 31 -5000 150 300 R 50 50 1 1 I
|
|
X PE10/FSMC_D7/TIM1_CH2N/EVENTOUT 41 5000 1550 300 L 50 50 1 1 I
|
|
X PB12/SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN/CAN2_RX/OTG_HS_ULPI_D5/ETH_RMII_TXD0/ETH_MII_TXD0/OTG_HS_ID/EVENTOUT 51 -5000 -2250 300 R 50 50 1 1 I
|
|
X PD14/FSMC_D0/TIM4_CH3/EVENTOUT/_EVENTOUT 61 5000 -650 300 L 50 50 1 1 I
|
|
X PA12/USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP/EVENTOUT 71 -5000 -450 300 R 50 50 1 1 I
|
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X PD0/FSMC_D2/CAN1_RX/EVENTOUT 81 5000 750 300 L 50 50 1 1 I
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X PB5/I2C1_SMBA/CAN2_RX/OTG_HS_ULPI_D7/ETH_PPS_OUT/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/DCMI_D10/I2S3_SD/EVENTOUT 91 -5000 -1550 300 R 50 50 1 1 I
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X PH0/OSC_IN/EVENTOUT 12 -5000 2150 300 R 50 50 1 1 I
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X VDDA 22 -1750 3000 300 D 50 50 1 1 I
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X PA7/SPI1_MOSI/TIM8_CH1N/TIM14_CH1/TIM3_CH2/ETH_MII_RX_DV/TIM1_CH1N/RMII_CRS_DV/EVENTOUT 32 -5000 50 300 R 50 50 1 1 I
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X PE11/FSMC_D8/TIM1_CH2/EVENTOUT 42 5000 1450 300 L 50 50 1 1 I
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X PB13/SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N/CAN2_TX/OTG_HS_ULPI_D6/ETH_RMII_TXD1/ETH_MII_TXD1/EVENTOUT 52 -5000 -2350 300 R 50 50 1 1 I
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X PD15/FSMC_D1/TIM4_CH4/EVENTOUT 62 5000 -750 300 L 50 50 1 1 I
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X PA13/JTMS/SWDIO/EVENTOUT 72 -5000 -550 300 R 50 50 1 1 I
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X PD1/FSMC_D3/CAN1_TX/EVENTOUT 82 5000 650 300 L 50 50 1 1 I
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X PB6/I2C1_SCL/TIM4_CH1/CAN2_TX/DCMI_D5/USART1_TX/EVENTOUT 92 -5000 -1650 300 R 50 50 1 1 I
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X PH1/OSC_OUT/EVENTOUT 13 -5000 1550 300 R 50 50 1 1 I
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X PA0/WKUP/USART2_CTS/UART4_TX/ETH_MII_CRS_/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR/EVENTOUT 23 -5000 750 300 R 50 50 1 1 I
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X PC4/ETH_RMII_RX_D0/ETH_MII_RX_D0/EVENTOUT 33 5000 -1450 300 L 50 50 1 1 I
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X PE12/FSMC_D9/TIM1_CH3N/EVENTOUT 43 5000 1350 300 L 50 50 1 1 I
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X PB14/SPI2_MISO/TIM1_CH2N/TIM12_CH1/OTG_HS_DM/USART3_RTS/TIM8_CH2N/I2S2ext_SD/EVENTOUT 53 -5000 -2450 300 R 50 50 1 1 I
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X PC6/I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/DCMI_D0/TIM3_CH1/EVENTOUT 63 5000 -1650 300 L 50 50 1 1 I
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X VCAP_2 73 1400 -3000 300 U 50 50 1 1 I
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X PD2/TIM3_ETR/UART5_RX/SDIO_CMD/DCMI_D11/EVENTOUT 83 5000 550 300 L 50 50 1 1 I
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X PB7/I2C1_SDA/FSMC_NL/DCMI_VSYNC/USART1_RX/TIM4_CH2/EVENTOUT 93 -5000 -1750 300 R 50 50 1 1 I
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X NRST 14 -5000 2350 300 R 50 50 1 1 I
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X PA1/USART2_RTS/UART4_RX/ETH_RMII_REF_CLK/ETH_MII_RX_CLK/TIM5_CH2/TIMM2_CH2/EVENTOUT 24 -5000 650 300 R 50 50 1 1 I
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X PC5/ETH_RMII_RX_D1/ETH_MII_RX_D1/EVENTOUT 34 5000 -1550 300 L 50 50 1 1 I
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X PE13/FSMC_D10/TIM1_CH3/EVENTOUT 44 5000 1250 300 L 50 50 1 1 I
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X PB15/SPI2_MOSI/I2S2_SD/TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP/EVENTOUT 54 -5000 -2550 300 R 50 50 1 1 I
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X PC7/I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/DCMI_D1/TIM3_CH2/EVENTOUT 64 5000 -1750 300 L 50 50 1 1 I
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X VSS 74 200 -3000 300 U 50 50 1 1 I
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|
X PD3/FSMC_CLK/USART2_CTS/EVENTOUT 84 5000 450 300 L 50 50 1 1 I
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X BOOT0 94 -5000 2550 300 R 50 50 1 1 I
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X PC0/OTG_HS_ULPI_STP/EVENTOUT 15 5000 -1050 300 L 50 50 1 1 I
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X PA2/USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3/ETH_MDIO/EVENTOUT 25 -5000 550 300 R 50 50 1 1 I
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X PB0/TIM3_CH3/TIM8_CH2N/OTG_HS_ULPI_D1/ETH_MII_RXD2/TIM1_CH2N/EVENTOUT 35 -5000 -1050 300 R 50 50 1 1 I
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X PE14/FSMC_D11/TIM1_CH4/EVENTOUT 45 5000 1150 300 L 50 50 1 1 I
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X PD8/FSMC_D13/USART3_TX/EVENTOUT 55 5000 -50 300 L 50 50 1 1 I
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X PC8/TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK/DCMI_D2/EVENTOUT 65 5000 -1850 300 L 50 50 1 1 I
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X VDD 75 450 3000 300 D 50 50 1 1 I
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X PD4/FSMC_NOE/USART2_RTS/EVENTOUT 85 5000 350 300 L 50 50 1 1 I
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X PB8/TIM4_CH3/SDIO_D4/TIM10_CH1/DCMI_D6/ETH_MII_TXD3/I2C1_SCL/CAN1_RX/EVENTOUT 95 -5000 -1850 300 R 50 50 1 1 I
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X PC1/ETH_MDC/_EVENTOUT 16 5000 -1150 300 L 50 50 1 1 I
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X PA3/USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/OTG_HS_ULPI_D0/ETH_MII_COL/EVENTOUT 26 -5000 450 300 R 50 50 1 1 I
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X PB1/TIM3_CH4/TIM8_CH3N/OTG_HS_ULPI_D2/ETH_MII_RXD3/OTG_HS_INTN/TIM1_CH3N/EVENTOUT 36 -5000 -1150 300 R 50 50 1 1 I
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X PE15/FSMC_D12/TIM1_BKIN/EVENTOUT 46 5000 1050 300 L 50 50 1 1 I
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|
X PD9/FSMC_D14/USART3_RX/EVENTOUT 56 5000 -150 300 L 50 50 1 1 I
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X PC9/I2S_CKIN/MCO2/TIM8_CH4/SDIO_D1/I2C3_SDA/DCMI_D3/TIM3_CH4/EVENTOUT 66 5000 -1950 300 L 50 50 1 1 I
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X PA14/JTCK/SWCLK/EVENTOUT 76 -5000 -650 300 R 50 50 1 1 I
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X PD5/FSMC_NWE/USART2_TX/EVENTOUT 86 5000 250 300 L 50 50 1 1 I
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X PB9/SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/DCMI_D7/I2C1_SDA/CAN1_TX/EVENTOUT 96 -5000 -1950 300 R 50 50 1 1 I
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X PC2/SPI2_MISO/OTG_HS_ULPI_DIR/ETH_MII_TXD2/I2S2ext_SD/EVENTOUT 17 5000 -1250 300 L 50 50 1 1 I
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X VSS 27 0 -3000 300 U 50 50 1 1 I
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X PB2/BOOT1/EVENTOUT 37 -5000 -1250 300 R 50 50 1 1 I
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X PB10/SPI2_SCK/I2S2_CK/I2C2_SCL/USART3_TX/OTG_HS_ULPI_D3/ETH_MII_RX_ER/TIM2_CH3/EVENTOUT 47 -5000 -2050 300 R 50 50 1 1 I
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X PD10/FSMC_D15/USART3_CK/EVENTOUT 57 5000 -250 300 L 50 50 1 1 I
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X PA8/MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF/EVENTOUT 67 -5000 -50 300 R 50 50 1 1 I
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|
X PA15/JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS/EVENTOUT 77 -5000 -750 300 R 50 50 1 1 I
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X PD6/FSMC_NWAIT/USART2_RX/EVENTOUT 87 5000 150 300 L 50 50 1 1 I
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X PE0/TIM4_ETR/FSMC_NBL0/DCMI_D2/EVENTOUT 97 5000 2550 300 L 50 50 1 1 I
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|
X PC3/SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT/ETH_MII_TX_CLK/EVENTOUT 18 5000 -1350 300 L 50 50 1 1 I
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|
X VDD 28 -150 3000 300 D 50 50 1 1 I
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X PE7/FSMC_D4/TIM1_ETR/EVENTOUT 38 5000 1850 300 L 50 50 1 1 I
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X PB11/I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4/ETH_RMII_TX_EN/ETH_MII_TX_EN/TIM2_CH4/EVENTOUT 48 -5000 -2150 300 R 50 50 1 1 I
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X PD11/FSMC_CLE/FSMC_A16/USART3_CTS/EVENTOUT 58 5000 -350 300 L 50 50 1 1 I
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X PA9/USART1_TX/TIM1_CH2/I2C3_SMBA/DCMI_D0/EVENTOUT 68 -5000 -150 300 R 50 50 1 1 I
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X PC10/SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/DCMI_D8/USART3_TX/EVENTOUT 78 5000 -2050 300 L 50 50 1 1 I
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X PD7/USART2_CK/FSMC_NE1/FSMC_NCE2/EVENTOUT 88 5000 50 300 L 50 50 1 1 I
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X PE1/FSMC_NBL1/DCMI_D3/EVENTOUT 98 5000 2450 300 L 50 50 1 1 I
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|
X VDD 19 -450 3000 300 D 50 50 1 1 I
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X PA4/SPI1_NSS/SPI3_NSS/USART2_CK/DCMI_HSYNC/OTG_HS_SOF/I2S3_WS/EVENTOUT 29 -5000 350 300 R 50 50 1 1 I
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X PE8/FSMC_D5/TIM1_CH1N/EVENTOUT 39 5000 1750 300 L 50 50 1 1 I
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X VCAP_1 49 900 -3000 300 U 50 50 1 1 I
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X PD12/FSMC_ALE/FSMC_A17/TIM4_CH1/USART3_RTS/EVENTOUT 59 5000 -450 300 L 50 50 1 1 I
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X PA10/USART1_RX/TIM1_CH3/OTG_FS_ID/DCMI_D1/EVENTOUT 69 -5000 -250 300 R 50 50 1 1 I
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X PC11/UART4_RX/SPI3_MISO/SDIO_D3/DCMI_D4/USART3_RX/I2S3ext_SD/EVENTOUT 79 5000 -2150 300 L 50 50 1 1 I
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X PB3/JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK/EVENTOUT 89 -5000 -1350 300 R 50 50 1 1 I
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X VSS 99 400 -3000 300 U 50 50 1 1 I
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|
X VDD 100 750 3000 300 D 50 50 1 1 I
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ENDDRAW
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ENDDEF
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#
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#End Library
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