diff --git a/template/raspberrypi-gpio/meta/brd.png b/template/raspberrypi-gpio/meta/brd.png new file mode 100755 index 00000000..a8e140f7 Binary files /dev/null and b/template/raspberrypi-gpio/meta/brd.png differ diff --git a/template/raspberrypi-gpio/meta/icon.png b/template/raspberrypi-gpio/meta/icon.png new file mode 100755 index 00000000..5e5707e9 Binary files /dev/null and b/template/raspberrypi-gpio/meta/icon.png differ diff --git a/template/raspberrypi-gpio/meta/info.html b/template/raspberrypi-gpio/meta/info.html new file mode 100755 index 00000000..f641c66c --- /dev/null +++ b/template/raspberrypi-gpio/meta/info.html @@ -0,0 +1,25 @@ + + +Raspberry Pi - Expansion Board + + +

Raspberry Pi

+

Expansion Board

+ +

This project template is the basis of an expansion board for the +Raspberry Pi $25 ARM +board.

+ +

This base project includes a PCB edge defined as the same size as the +Raspberry-Pi PCB with the connectors placed correctly to align the two boards. +All IO present on the Raspberry-Pi board is connected to the project through the +0.1" expansion headers.

+ +

The board outline looks like the following:

+ +

+ +

(c)2012 Brian Sidebotham
+(c)2012 Kicad Developers

+ + diff --git a/template/raspberrypi-gpio/raspberrypi-gpio-cache.lib b/template/raspberrypi-gpio/raspberrypi-gpio-cache.lib new file mode 100755 index 00000000..e5e7f0c5 --- /dev/null +++ b/template/raspberrypi-gpio/raspberrypi-gpio-cache.lib @@ -0,0 +1,76 @@ +EESchema-LIBRARY Version 2.3 Date: 15/11/2012 21:22:43 +#encoding utf-8 +# +# +3.3V +# +DEF +3.3V #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -40 30 H I C CNN +F1 "+3.3V" 0 110 30 H V C CNN +ALIAS +3,3V +DRAW +X +3.3V 1 0 0 0 U 30 30 0 0 W N +C 0 60 20 0 1 0 N +P 3 0 1 0 0 0 0 40 0 40 N +ENDDRAW +ENDDEF +# +# +5V +# +DEF +5V #PWR 0 40 Y Y 1 F P +F0 "#PWR" 0 90 20 H I C CNN +F1 "+5V" 0 90 30 H V C CNN +DRAW +X +5V 1 0 0 0 U 20 20 0 0 W N +C 0 50 20 0 1 0 N +P 4 0 1 0 0 0 0 30 0 30 0 30 N +ENDDRAW +ENDDEF +# +# CONN_13X2 +# +DEF CONN_13X2 P 0 10 Y N 1 F N +F0 "P" 0 700 60 H V C CNN +F1 "CONN_13X2" 0 0 50 V V C CNN +DRAW +S -100 650 100 -650 0 1 0 N +X P1 1 -400 600 300 R 40 30 1 1 P I +X P2 2 400 600 300 L 40 30 1 1 P I +X P3 3 -400 500 300 R 40 30 1 1 P I +X P4 4 400 500 300 L 40 30 1 1 P I +X P5 5 -400 400 300 R 40 30 1 1 P I +X P6 6 400 400 300 L 40 30 1 1 P I +X P7 7 -400 300 300 R 40 30 1 1 P I +X P8 8 400 300 300 L 40 30 1 1 P I +X P9 9 -400 200 300 R 40 30 1 1 P I +X P10 10 400 200 300 L 40 30 1 1 P I +X P20 20 400 -300 300 L 40 30 1 1 P I +X P11 11 -400 100 300 R 40 30 1 1 P I +X P21 21 -400 -400 300 R 40 30 1 1 P I +X P12 12 400 100 300 L 40 30 1 1 P I +X P22 22 400 -400 300 L 40 30 1 1 P I +X P13 13 -400 0 300 R 40 30 1 1 P I +X P23 23 -400 -500 300 R 40 30 1 1 P I +X P14 14 400 0 300 L 40 30 1 1 P I +X P20 24 400 -500 300 L 40 30 1 1 P I +X P15 15 -400 -100 300 R 40 30 1 1 P I +X P24 25 -400 -600 300 R 40 30 1 1 P I +X P16 16 400 -100 300 L 40 30 1 1 P I +X P22 26 400 -600 300 L 40 30 1 1 P I +X P17 17 -400 -200 300 R 40 30 1 1 P I +X P18 18 400 -200 300 L 40 30 1 1 P I +X P19 19 -400 -300 300 R 40 30 1 1 P I +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/template/raspberrypi-gpio/raspberrypi-gpio.cmp b/template/raspberrypi-gpio/raspberrypi-gpio.cmp new file mode 100755 index 00000000..ade21134 --- /dev/null +++ b/template/raspberrypi-gpio/raspberrypi-gpio.cmp @@ -0,0 +1,10 @@ +Cmp-Mod V01 Created by CvPcb (2012-11-15 BZR 3804)-testing date = 15/11/2012 21:23:25 + +BeginCmp +TimeStamp = /50A55ABA; +Reference = P1; +ValeurCmp = CONN_13X2; +IdModule = pin_array_13x2; +EndCmp + +EndListe diff --git a/template/raspberrypi-gpio/raspberrypi-gpio.kicad_pcb b/template/raspberrypi-gpio/raspberrypi-gpio.kicad_pcb new file mode 100755 index 00000000..ae9499ce --- /dev/null +++ b/template/raspberrypi-gpio/raspberrypi-gpio.kicad_pcb @@ -0,0 +1,299 @@ +(kicad_pcb (version 3) (host pcbnew "(2012-11-30 BZR 3829)-testing") + + (general + (links 0) + (no_connects 0) + (area 127.606667 112.000001 242.964763 190.8) + (thickness 1.6) + (drawings 41) + (tracks 0) + (zones 0) + (modules 1) + (nets 4) + ) + + (page A3) + (title_block + (date "15 nov 2012") + ) + + (layers + (15 F.Cu signal) + (0 B.Cu signal) + (16 B.Adhes user) + (17 F.Adhes user) + (18 B.Paste user) + (19 F.Paste user) + (20 B.SilkS user) + (21 F.SilkS user) + (22 B.Mask user) + (23 F.Mask user) + (24 Dwgs.User user) + (25 Cmts.User user) + (26 Eco1.User user) + (27 Eco2.User user) + (28 Edge.Cuts user) + ) + + (setup + (last_trace_width 0.2) + (trace_clearance 0.2) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.1524) + (segment_width 0.2) + (edge_width 0.15) + (via_size 0.9) + (via_drill 0.6) + (via_min_size 0.8) + (via_min_drill 0.5) + (uvia_size 0.5) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.5) + (uvia_min_drill 0.1) + (pcb_text_width 0.3) + (pcb_text_size 1 1) + (mod_edge_width 0.15) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1 1) + (pad_drill 0.6) + (pad_to_mask_clearance 0) + (aux_axis_origin 143.5 181) + (visible_elements 7FFFFFFF) + (pcbplotparams + (layerselection 3178497) + (usegerberextensions true) + (excludeedgelayer true) + (linewidth 152400) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15) + (hpglpenoverlay 2) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotothertext true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 +3.3V) + (net 2 +5V) + (net 3 GND) + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.2) + (via_dia 0.9) + (via_drill 0.6) + (uvia_dia 0.5) + (uvia_drill 0.1) + (add_net "") + (add_net +3.3V) + (add_net +5V) + (add_net GND) + ) + + (net_class Power "" + (clearance 0.2) + (trace_width 0.5) + (via_dia 1) + (via_drill 0.7) + (uvia_dia 0.5) + (uvia_drill 0.1) + ) + + (module pin_array_13x2 (layer F.Cu) (tedit 50A55E7A) (tstamp 50A55DA3) + (at 161 129) + (descr "Double rangee de contacts 2 x 12 pins") + (tags CONN) + (path /50A55ABA) + (fp_text reference P1 (at -15.5 4) (layer F.SilkS) + (effects (font (size 1.016 1.016) (thickness 0.2032))) + ) + (fp_text value CONN_13X2 (at 12 4) (layer F.SilkS) + (effects (font (size 1.016 1.016) (thickness 0.2032))) + ) + (fp_line (start -16.51 2.54) (end 16.51 2.54) (layer F.SilkS) (width 0.2032)) + (fp_line (start 16.51 -2.54) (end -16.51 -2.54) (layer F.SilkS) (width 0.2032)) + (fp_line (start -16.51 -2.54) (end -16.51 2.54) (layer F.SilkS) (width 0.2032)) + (fp_line (start 16.51 2.54) (end 16.51 -2.54) (layer F.SilkS) (width 0.2032)) + (pad 1 thru_hole rect (at -15.24 1.27) (size 1.524 1.524) (drill 0.8128) + (layers *.Cu *.Mask F.SilkS) + (net 1 +3.3V) + ) + (pad 2 thru_hole circle (at -15.24 -1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + (net 2 +5V) + ) + (pad 3 thru_hole circle (at -12.7 1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 4 thru_hole circle (at -12.7 -1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 5 thru_hole circle (at -10.16 1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 6 thru_hole circle (at -10.16 -1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + (net 3 GND) + ) + (pad 7 thru_hole circle (at -7.62 1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 8 thru_hole circle (at -7.62 -1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 9 thru_hole circle (at -5.08 1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 10 thru_hole circle (at -5.08 -1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 11 thru_hole circle (at -2.54 1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 12 thru_hole circle (at -2.54 -1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 13 thru_hole circle (at 0 1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 14 thru_hole circle (at 0 -1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 15 thru_hole circle (at 2.54 1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 16 thru_hole circle (at 2.54 -1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 17 thru_hole circle (at 5.08 1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 18 thru_hole circle (at 5.08 -1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 19 thru_hole circle (at 7.62 1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 20 thru_hole circle (at 7.62 -1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 21 thru_hole circle (at 10.16 1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 22 thru_hole circle (at 10.16 -1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 23 thru_hole circle (at 12.7 1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 24 thru_hole circle (at 12.7 -1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 25 thru_hole circle (at 15.24 1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 26 thru_hole circle (at 15.24 -1.27) (size 1.524 1.524) (drill 1.016) + (layers *.Cu *.Mask F.SilkS) + ) + (model pin_array/pins_array_13x2.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (gr_text "RASPBERRY-PI ADDON BOARD\nVIEW FROM TOP\nNOTE: P1 SHOULD BE FITTED ON THE REVERSE OF THE BOARD" (at 144 183.5) (layer Dwgs.User) + (effects (font (size 2 1.7) (thickness 0.12)) (justify left)) + ) + (dimension 56 (width 0.12) (layer Dwgs.User) + (gr_text "56.000 mm" (at 132 153 90) (layer Dwgs.User) + (effects (font (size 1 1) (thickness 0.12))) + ) + (feature1 (pts (xy 143.5 125) (xy 131 125))) + (feature2 (pts (xy 143.5 181) (xy 131 181))) + (crossbar (pts (xy 133 181) (xy 133 125))) + (arrow1a (pts (xy 133 125) (xy 133.58642 126.126503))) + (arrow1b (pts (xy 133 125) (xy 132.41358 126.126503))) + (arrow2a (pts (xy 133 181) (xy 133.58642 179.873497))) + (arrow2b (pts (xy 133 181) (xy 132.41358 179.873497))) + ) + (dimension 85 (width 0.12) (layer Dwgs.User) + (gr_text "85.000 mm" (at 186 113.000001) (layer Dwgs.User) + (effects (font (size 1 1) (thickness 0.12))) + ) + (feature1 (pts (xy 228.5 125) (xy 228.5 112.000001))) + (feature2 (pts (xy 143.5 125) (xy 143.5 112.000001))) + (crossbar (pts (xy 143.5 114.000001) (xy 228.5 114.000001))) + (arrow1a (pts (xy 228.5 114.000001) (xy 227.373497 114.586421))) + (arrow1b (pts (xy 228.5 114.000001) (xy 227.373497 113.413581))) + (arrow2a (pts (xy 143.5 114.000001) (xy 144.626503 114.586421))) + (arrow2b (pts (xy 143.5 114.000001) (xy 144.626503 113.413581))) + ) + (gr_text "RCA\nREMOVE WITH\nSTD HEADERS\n!NO TH ABOVE!" (at 188.5 118) (layer Dwgs.User) + (effects (font (size 1 1) (thickness 0.12))) + ) + (gr_text "1/8\" JACK\nOK WITH STD\nHEADERS\n!NO TH ABOVE!" (at 207.5 118) (layer Dwgs.User) + (effects (font (size 1 1) (thickness 0.12))) + ) + (gr_line (start 228.5 142) (end 228.5 125) (angle 90) (layer Edge.Cuts) (width 0.15)) + (gr_line (start 217.5 142) (end 228.5 142) (angle 90) (layer Edge.Cuts) (width 0.15)) + (gr_line (start 217.5 157) (end 217.5 142) (angle 90) (layer Edge.Cuts) (width 0.15)) + (gr_line (start 228.5 157) (end 217.5 157) (angle 90) (layer Edge.Cuts) (width 0.15)) + (gr_line (start 228.5 181) (end 228.5 157) (angle 90) (layer Edge.Cuts) (width 0.15)) + (gr_text "DOUBLE USB\nCUTOUT FOR ALL\nBOARDS" (at 236.5 149) (layer Dwgs.User) + (effects (font (size 1 1) (thickness 0.12))) + ) + (gr_text "RJ45\nCUTOUT FOR STD\nHEADERS\n!NO TH ABOVE!" (at 236.5 170) (layer Dwgs.User) + (effects (font (size 1 1) (thickness 0.12))) + ) + (gr_line (start 207.5 181) (end 228.5 162) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 207.5 162) (end 228.5 181) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 207.5 162) (end 228.5 162) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 207.5 181) (end 207.5 162) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 228.5 181) (end 207.5 181) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 228.5 162) (end 228.5 181) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 217.5 157) (end 228.5 142) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 217.5 142) (end 228.5 157) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 217.5 142) (end 228.5 142) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 217.5 157) (end 217.5 142) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 228.5 157) (end 217.5 157) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 228.5 142) (end 228.5 157) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 182.5 125) (end 194.5 139) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 182.5 139) (end 194.5 125) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 194.5 139) (end 194.5 138) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 182.5 139) (end 194.5 139) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 182.5 138) (end 182.5 139) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 214.5 125) (end 200.5 138) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 200.5 125) (end 214.5 138) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 200.5 138) (end 200.5 125) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 214.5 138) (end 200.5 138) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 214.5 125) (end 214.5 138) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 200.5 125) (end 214.5 125) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 194.5 125) (end 182.5 125) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 194.5 138) (end 194.5 125) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 182.5 125) (end 182.5 138) (angle 90) (layer Dwgs.User) (width 0.2)) + (gr_line (start 228.5 125) (end 143.5 125) (angle 90) (layer Edge.Cuts) (width 0.15)) + (gr_line (start 143.5 181) (end 228.5 181) (angle 90) (layer Edge.Cuts) (width 0.15)) + (gr_line (start 143.5 125) (end 143.5 181) (angle 90) (layer Edge.Cuts) (width 0.15)) + + + +) diff --git a/template/raspberrypi-gpio/raspberrypi-gpio.net b/template/raspberrypi-gpio/raspberrypi-gpio.net new file mode 100755 index 00000000..ff5df3ec --- /dev/null +++ b/template/raspberrypi-gpio/raspberrypi-gpio.net @@ -0,0 +1,35 @@ +# EESchema Netlist Version 1.1 created 15/11/2012 21:22:35 +( + ( /50A55ABA $noname P1 CONN_13X2 {Lib=CONN_13X2} + ( 1 +3.3V ) + ( 2 +5V ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 6 GND ) + ( 7 ? ) + ( 8 ? ) + ( 9 ? ) + ( 10 ? ) + ( 11 ? ) + ( 12 ? ) + ( 13 ? ) + ( 14 ? ) + ( 15 ? ) + ( 16 ? ) + ( 17 ? ) + ( 18 ? ) + ( 19 ? ) + ( 20 ? ) + ( 21 ? ) + ( 22 ? ) + ( 23 ? ) + ( 24 ? ) + ( 25 ? ) + ( 26 ? ) + ) +) +* +{ Pin List by Nets +} +#End diff --git a/template/raspberrypi-gpio/raspberrypi-gpio.pro b/template/raspberrypi-gpio/raspberrypi-gpio.pro new file mode 100755 index 00000000..93c40c4f --- /dev/null +++ b/template/raspberrypi-gpio/raspberrypi-gpio.pro @@ -0,0 +1,145 @@ +update=15/11/2012 21:11:59 +version=1 +last_client=kicad +[cvpcb] +version=1 +NetITyp=0 +NetIExt=.net +PkgIExt=.pkg +NetDir= +LibDir= +NetType=0 +[cvpcb/libraries] +EquName1=devcms +[pcbnew] +version=1 +PadDrlX=320 +PadDimH=600 +PadDimV=600 +PadForm=1 +PadMask=14745599 +ViaDiam=450 +ViaDril=250 +Isol=60 +Countlayer=2 +Lpiste=170 +RouteTo=15 +RouteBo=0 +TypeVia=3 +Segm45=1 +Racc45=1 +Unite=0 +SegFill=1 +SegAffG=0 +NewAffG=1 +PadFill=1 +PadAffG=1 +PadSNum=1 +ModAffC=0 +ModAffT=0 +PcbAffT=0 +SgPcb45=1 +TxtPcbV=800 +TxtPcbH=600 +TxtModV=600 +TxtModH=600 +TxtModW=120 +HPGLnum=1 +HPGdiam=15 +HPGLSpd=20 +HPGLrec=2 +HPGLorg=0 +GERBmin=15 +VEgarde=100 +DrawLar=150 +EdgeLar=150 +TxtLar=120 +MSegLar=150 +ForPlot=1 +WpenSer=10 +UserGrX=0,01 +UserGrY=0,01 +UserGrU=1 +DivGrPc=1 +TimeOut=600 +MaxLnkS=3 +ShowRat=0 +ShowMRa=1 +[pcbnew/libraries] +LibDir= +LibName1=sockets +LibName2=connect +LibName3=discret +LibName4=pin_array +LibName5=divers +LibName6=libcms +LibName7=display +LibName8=valves +LibName9=led +LibName10=dip_sockets +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +SimCmd= +UseNetN=0 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +[general] +version=1 diff --git a/template/raspberrypi-gpio/raspberrypi-gpio.sch b/template/raspberrypi-gpio/raspberrypi-gpio.sch new file mode 100755 index 00000000..fb626f95 --- /dev/null +++ b/template/raspberrypi-gpio/raspberrypi-gpio.sch @@ -0,0 +1,169 @@ +EESchema Schematic File Version 2 date 15/11/2012 21:22:43 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:rpi-cache +EELAYER 27 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 nov 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L CONN_13X2 P1 +U 1 1 50A55ABA +P 2400 1800 +F 0 "P1" H 2400 2500 60 0000 C CNN +F 1 "CONN_13X2" V 2400 1800 50 0000 C CNN + 1 2400 1800 + 1 0 0 -1 +$EndComp +$Comp +L +3.3V #PWR01 +U 1 1 50A55B18 +P 1900 1050 +F 0 "#PWR01" H 1900 1010 30 0001 C CNN +F 1 "+3.3V" H 1900 1160 30 0000 C CNN + 1 1900 1050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1900 1050 1900 1200 +Wire Wire Line + 1900 1200 2000 1200 +$Comp +L +5V #PWR02 +U 1 1 50A55B2E +P 2900 1050 +F 0 "#PWR02" H 2900 1140 20 0001 C CNN +F 1 "+5V" H 2900 1140 30 0000 C CNN + 1 2900 1050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2900 1050 2900 1200 +Wire Wire Line + 2900 1200 2800 1200 +NoConn ~ 2800 1300 +Wire Wire Line + 2000 1300 1250 1300 +Wire Wire Line + 2000 1400 1250 1400 +Text Label 1250 1300 0 60 ~ 0 +GPIO0(SDA) +Text Label 1250 1400 0 60 ~ 0 +GPIO1(SCL) +Wire Wire Line + 2000 1500 1250 1500 +Text Label 1250 1500 0 60 ~ 0 +GPIO4 +NoConn ~ 2000 1600 +Wire Wire Line + 2000 1700 1250 1700 +Wire Wire Line + 2000 1800 1250 1800 +Wire Wire Line + 2000 1900 1250 1900 +Text Label 1250 1700 0 60 ~ 0 +GPIO17 +Text Label 1250 1800 0 60 ~ 0 +GPIO21 +Text Label 1250 1900 0 60 ~ 0 +GPIO22 +NoConn ~ 2000 2000 +Wire Wire Line + 2000 2100 1250 2100 +Wire Wire Line + 2000 2200 1250 2200 +Wire Wire Line + 2000 2300 1250 2300 +Text Label 1250 2100 0 60 ~ 0 +GPIO10(MOSI) +Text Label 1250 2200 0 60 ~ 0 +GPIO9(MISO) +Text Label 1250 2300 0 60 ~ 0 +GPIO11(SCLK) +NoConn ~ 2000 2400 +$Comp +L GND #PWR03 +U 1 1 50A55C3F +P 2900 2500 +F 0 "#PWR03" H 2900 2500 30 0001 C CNN +F 1 "GND" H 2900 2430 30 0001 C CNN + 1 2900 2500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2900 2500 2900 1400 +Wire Wire Line + 2900 1400 2800 1400 +Wire Wire Line + 2800 1500 3500 1500 +Wire Wire Line + 2800 1600 3500 1600 +Text Label 3500 1500 2 60 ~ 0 +TXD +Text Label 3500 1600 2 60 ~ 0 +RXD +Wire Wire Line + 2800 1700 3500 1700 +Text Label 3500 1700 2 60 ~ 0 +GPIO18 +NoConn ~ 2800 1800 +Wire Wire Line + 2800 1900 3500 1900 +Wire Wire Line + 2800 2000 3500 2000 +Text Label 3500 1900 2 60 ~ 0 +GPIO23 +Text Label 3500 2000 2 60 ~ 0 +GPIO24 +NoConn ~ 2800 2100 +Wire Wire Line + 2800 2200 3500 2200 +Text Label 3500 2200 2 60 ~ 0 +GPIO25 +Wire Wire Line + 2800 2300 3500 2300 +Wire Wire Line + 2800 2400 3500 2400 +Text Label 3500 2300 2 60 ~ 0 +GPIO8(CE0) +Text Label 3500 2400 2 60 ~ 0 +GPIO7(CE1) +$EndSCHEMATC diff --git a/template/raspberrypi-gpio/raspberrypi-gpio.stf b/template/raspberrypi-gpio/raspberrypi-gpio.stf new file mode 100755 index 00000000..c4a0667d --- /dev/null +++ b/template/raspberrypi-gpio/raspberrypi-gpio.stf @@ -0,0 +1 @@ +comp = "P1" module = "HE10_26D"