Added STM32F407R as well. Also removed the (seemingly not useful?) EVENTOUT description from every single GPIO pin to keep the symbol size reasonable.
This commit is contained in:
Scott
parent
cf7cd88aec
commit
e39f31b2a2
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@ -1,4 +1,4 @@
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EESchema-DOCLIB Version 2.0
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EESchema-DOCLIB Version 2.0 Date: Wed 12 Aug 2015 02:20:09 PM EDT
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#
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$CMP STM32F050C4
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D STM32F050C4, 32-bit ARM Cortex-M0 Microcontroller, 48MHz, 16KB Flash, 4KB RAM, RTC, VQFP48
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@ -1,4 +1,4 @@
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EESchema-LIBRARY Version 2.3
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EESchema-LIBRARY Version 2.3 Date: Wed 12 Aug 2015 02:20:09 PM EDT
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#encoding utf-8
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#
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# STM32F050C4
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@ -7,7 +7,7 @@ DEF STM32F050C4 U 0 40 Y Y 1 F N
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F0 "U" -1500 1900 60 H V C CNN
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F1 "STM32F050C4" 1250 -1900 60 H V C CNN
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F2 "LQFP48" 0 0 40 H V C CIN
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F3 "" 0 0 60 H V C CNN
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F3 "~" 0 0 60 H V C CNN
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ALIAS STM32F050C6
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DRAW
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S -1550 1850 1550 -1850 0 1 10 f
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@ -68,7 +68,7 @@ DEF STM32F050K4 U 0 40 Y Y 1 F N
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F0 "U" -1400 1450 60 H V C CNN
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F1 "STM32F050K4" 1150 -1450 60 H V C CNN
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F2 "LQFP32" 0 0 40 H V C CIN
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F3 "" 0 0 60 H V C CNN
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F3 "~" 0 0 60 H V C CNN
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ALIAS STM32F050K6
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DRAW
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S -1450 1400 1450 -1400 0 1 10 f
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@ -113,7 +113,7 @@ DEF STM32F100C4 U 0 40 Y Y 1 F N
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F0 "U" -1300 1650 60 H V C CNN
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F1 "STM32F100C4" 1050 -1650 60 H V C CNN
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F2 "LQFP48" 0 0 40 H V C CIN
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F3 "" 0 0 60 H V C CNN
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F3 "~" 0 0 60 H V C CNN
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ALIAS STM32F100C6
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DRAW
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S -1350 1600 1350 -1600 0 1 10 f
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@ -174,7 +174,7 @@ DEF STM32F100C8 U 0 40 Y Y 1 F N
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F0 "U" -1300 1650 60 H V C CNN
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F1 "STM32F100C8" 1050 -1650 60 H V C CNN
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F2 "LQFP48" 0 0 40 H V C CIN
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F3 "" 0 0 60 H V C CNN
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F3 "~" 0 0 60 H V C CNN
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ALIAS STM32F100CB
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DRAW
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S -1350 1600 1350 -1600 0 1 10 f
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@ -235,7 +235,7 @@ DEF STM32F100R4 U 0 40 Y Y 1 F N
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F0 "U" -1300 1950 60 H V C CNN
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F1 "STM32F100R4" 1050 -1900 60 H V C CNN
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F2 "LQFP64" 0 0 40 H V C CIN
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F3 "" 0 0 60 H V C CNN
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F3 "~" 0 0 60 H V C CNN
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ALIAS STM32F100R6
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DRAW
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S -1350 1900 1350 -1850 0 1 10 f
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@ -312,7 +312,7 @@ DEF STM32F100R8 U 0 40 Y Y 1 F N
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F0 "U" -1300 1950 60 H V C CNN
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F1 "STM32F100R8" 1050 -1900 60 H V C CNN
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F2 "LQFP64" 0 0 40 H V C CIN
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F3 "" 0 0 60 H V C CNN
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F3 "~" 0 0 60 H V C CNN
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ALIAS STM32F100RB
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DRAW
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S -1350 1900 1350 -1850 0 1 10 f
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@ -389,7 +389,7 @@ DEF STM32F100V8 U 0 40 Y Y 1 F N
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F0 "U" -1300 2800 60 H V C CNN
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F1 "STM32F100V8" 1050 -2800 60 H V C CNN
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F2 "LQFP100" 0 0 40 H V C CIN
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F3 "" 0 0 60 H V C CNN
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F3 "~" 0 0 60 H V C CNN
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ALIAS STM32F100VB
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DRAW
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S -1350 2750 1350 -2750 0 1 10 f
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@ -501,7 +501,7 @@ DEF STM32F103C4 U 0 40 Y Y 1 F N
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F0 "U" -1300 1650 50 H V C CNN
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F1 "STM32F103C4" 1050 -1650 50 H V C CNN
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F2 "LQFP48" 0 0 50 H V C CNN
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F3 "" 0 0 60 H V C CNN
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F3 "~" 0 0 60 H V C CNN
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ALIAS STM32F103C6
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DRAW
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S -1350 1600 1350 -1600 0 1 10 f
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@ -562,7 +562,7 @@ DEF STM32F103C8 U 0 40 Y Y 1 F N
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F0 "U" -1300 1650 50 H V C CNN
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F1 "STM32F103C8" 1050 -1650 50 H V C CNN
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F2 "LQFP48" 0 0 50 H V C CNN
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F3 "" 0 0 60 H V C CNN
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F3 "~" 0 0 60 H V C CNN
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ALIAS STM32F103CB
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DRAW
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S -1350 1600 1350 -1600 0 1 10 f
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@ -623,7 +623,7 @@ DEF STM32F103R4 U 0 40 Y Y 1 F N
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F0 "U" -1350 1950 50 H V C CNN
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F1 "STM32F103R4" 1150 -1950 50 H V C CNN
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F2 "LQFP64" 0 0 50 H V C CNN
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F3 "" 0 300 60 H V C CNN
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F3 "~" 0 300 60 H V C CNN
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ALIAS STM32F103R6
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DRAW
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S -1400 1900 1400 -1900 0 1 10 f
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@ -700,7 +700,7 @@ DEF STM32F103R8 U 0 40 Y Y 1 F N
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F0 "U" -1350 1950 50 H V C CNN
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F1 "STM32F103R8" 1150 -1950 50 H V C CNN
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F2 "LQFP64" 0 0 50 H V C CNN
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F3 "" 0 300 60 H V C CNN
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F3 "~" 0 300 60 H V C CNN
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ALIAS STM32F103RB
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DRAW
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S -1400 1900 1400 -1900 0 1 10 f
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@ -777,7 +777,7 @@ DEF STM32F103RC U 0 40 Y Y 1 F N
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F0 "U" -1350 1950 50 H V C CNN
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F1 "STM32F103RC" 1150 -1950 50 H V C CNN
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F2 "LQFP64" 0 0 50 H V C CNN
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F3 "" 0 300 60 H V C CNN
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F3 "~" 0 300 60 H V C CNN
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ALIAS STM32F103RD STM32F103RE
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DRAW
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S -1400 1900 1400 -1900 0 1 10 f
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@ -854,7 +854,7 @@ DEF STM32F103RF U 0 40 Y Y 1 F N
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F0 "U" -1350 1950 50 H V C CNN
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F1 "STM32F103RF" 1150 -1950 50 H V C CNN
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F2 "LQFP64" 0 0 50 H V C CNN
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F3 "" 0 300 60 H V C CNN
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F3 "~" 0 300 60 H V C CNN
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ALIAS STM32F103RG
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DRAW
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S -1400 1900 1400 -1900 0 1 10 f
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@ -931,7 +931,7 @@ DEF STM32F103V8 U 0 40 Y Y 1 F N
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F0 "U" -1350 2800 50 H V C CNN
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F1 "STM32F103V8" 1150 -2800 50 H V C CNN
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F2 "LQFP100" 0 0 50 H V C CNN
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F3 "" 0 1150 60 H V C CNN
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F3 "~" 0 1150 60 H V C CNN
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ALIAS STM32F103VB
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DRAW
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S -1400 2750 1400 -2750 0 1 10 f
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@ -1043,7 +1043,7 @@ DEF STM32F103VC U 0 40 Y Y 1 F N
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F0 "U" -1350 2800 50 H V C CNN
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F1 "STM32F103VC" 1150 -2800 50 H V C CNN
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F2 "LQFP100" 0 0 50 H V C CNN
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F3 "" 0 1150 60 H V C CNN
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F3 "~" 0 1150 60 H V C CNN
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ALIAS STM32F103VD STM32F103VE
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DRAW
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S -1400 2750 1400 -2750 0 1 10 f
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@ -1155,7 +1155,7 @@ DEF STM32F103VF U 0 40 Y Y 1 F N
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F0 "U" -1350 2800 50 H V C CNN
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F1 "STM32F103VF" 1150 -2800 50 H V C CNN
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F2 "LQFP100" 0 0 50 H V C CNN
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F3 "" 0 1150 60 H V C CNN
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F3 "~" 0 1150 60 H V C CNN
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ALIAS STM32F103VG
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DRAW
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S -1400 2750 1400 -2750 0 1 10 f
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@ -1267,7 +1267,7 @@ DEF STM32F105R8 U 0 40 Y Y 1 F N
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F0 "U" -2000 1900 60 H V C CNN
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F1 "STM32F105R8" 1750 -1900 60 H V C CNN
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F2 "LQFP64" 50 0 50 H V C CIN
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F3 "" 0 0 60 H V C CNN
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F3 "~" 0 0 60 H V C CNN
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ALIAS STM32F105RB STM32F105RC
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DRAW
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S -2050 1850 2050 -1850 0 1 10 f
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@ -1344,7 +1344,7 @@ DEF STM32F105V8 U 0 40 Y Y 1 F N
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F0 "U" -2000 2750 60 H V C CNN
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F1 "STM32F105V8" 1750 -2750 60 H V C CNN
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F2 "LQFP100" -50 0 50 H V C CIN
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F3 "" 0 0 60 H V C CNN
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F3 "~" 0 0 60 H V C CNN
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ALIAS STM32F105VB STM32F105VC
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DRAW
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S -2050 2700 2050 -2700 0 1 10 f
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@ -1456,7 +1456,7 @@ DEF STM32F107RB U 0 40 Y Y 1 F N
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F0 "U" -2000 1900 60 H V C CNN
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F1 "STM32F107RB" 1750 -1900 60 H V C CNN
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F2 "LQFP64" 50 0 50 H V C CIN
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F3 "" 0 0 60 H V C CNN
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F3 "~" 0 0 60 H V C CNN
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ALIAS STM32F107RC
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DRAW
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S -2050 1850 2050 -1850 0 1 10 f
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@ -1533,7 +1533,7 @@ DEF STM32F107VB U 0 40 Y Y 1 F N
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F0 "U" -2000 2750 60 H V C CNN
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F1 "STM32F107VB" 1750 -2750 60 H V C CNN
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F2 "LQFP100" -50 0 50 H V C CIN
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F3 "" 0 0 60 H V C CNN
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F3 "~" 0 0 60 H V C CNN
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ALIAS STM32F107VC
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DRAW
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S -2050 2700 2050 -2700 0 1 10 f
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@ -1645,76 +1645,76 @@ DEF STM32F405R U 0 40 Y Y 1 F N
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F0 "U" 100 -550 60 H V C CNN
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F1 "STM32F405R" 100 -450 60 H V C CNN
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F2 "TQFP64" 100 -650 60 H V C CNN
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F3 "" 100 -550 60 H V C CNN
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F3 "~" 100 -550 60 H V C CNN
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$FPLIST
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LQFP64
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$ENDFPLIST
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DRAW
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S -3300 -2100 3100 2000 0 1 0 f
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X VBAT 1 1000 2300 300 D 50 50 1 1 I
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X PC13/EVENTOUT 2 3400 -1500 300 L 50 50 1 1 I
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X PC14/OSC32_IN/EVENTOUT 3 3400 -1600 300 L 50 50 1 1 I
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X PC15/OSC32_OUT/EVENTOUT 4 3400 -1700 300 L 50 50 1 1 I
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X PH0/OSC_IN/EVENTOUT 5 -3600 1150 300 R 50 50 1 1 I
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X PH1/OSC_OUT/EVENTOUT 6 -3600 550 300 R 50 50 1 1 I
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X PC13 2 3400 -1500 300 L 50 50 1 1 I
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X PC14/OSC32_IN 3 3400 -1600 300 L 50 50 1 1 I
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X PC15/OSC32_OUT 4 3400 -1700 300 L 50 50 1 1 I
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X PH0/OSC_IN 5 -3600 1150 300 R 50 50 1 1 I
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X PH1/OSC_OUT 6 -3600 550 300 R 50 50 1 1 I
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X NRST 7 -3600 1350 300 R 50 50 1 1 I
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X PC0/OTG_HS_ULPI_STP/EVENTOUT 8 3400 -200 300 L 50 50 1 1 I
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X PC1/EVENTOUT 9 3400 -300 300 L 50 50 1 1 I
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X PC2/SPI2_MISO/OTG_HS_ULPI_DIR/I2S2ext_SD/EVENTOUT 10 3400 -400 300 L 50 50 1 1 I
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X PA4/SPI1_NSS/SPI3_NSS/USART2_CK/OTG_HS_SOF/I2S3_WS/EVENTOUT 20 -3600 -650 300 R 50 50 1 1 I
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X PB11/I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4/TIM2_CH4/EVENTOUT 30 3400 500 300 L 50 50 1 1 I
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X PC9/I2S_CKIN/MCO2/TIM8_CH4/SDIO_D1/I2C3_SDA/TIM3_CH4/EVENTOUT 40 3400 -1100 300 L 50 50 1 1 I
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X PA15/JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS/EVENTOUT 50 -3600 -1750 300 R 50 50 1 1 I
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X PC0/OTG_HS_ULPI_STP 8 3400 -200 300 L 50 50 1 1 I
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X PC1 9 3400 -300 300 L 50 50 1 1 I
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X PC2/SPI2_MISO/OTG_HS_ULPI_DIR/I2S2ext_SD 10 3400 -400 300 L 50 50 1 1 I
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X PA4/SPI1_NSS/SPI3_NSS/USART2_CK/OTG_HS_SOF/I2S3_WS 20 -3600 -650 300 R 50 50 1 1 I
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X PB11/I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4/TIM2_CH4 30 3400 500 300 L 50 50 1 1 I
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X PC9/I2S_CKIN/MCO2/TIM8_CH4/SDIO_D1/I2C3_SDA/TIM3_CH4 40 3400 -1100 300 L 50 50 1 1 I
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X PA15/JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS 50 -3600 -1750 300 R 50 50 1 1 I
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X BOOT0 60 -3600 1550 300 R 50 50 1 1 I
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X PC3/SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT/EVENTOUT 11 3400 -500 300 L 50 50 1 1 I
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X PA5/SPI1_SCK/OTG_HS_ULPI_CK/TIM2_CH1_ETR/TIM8_CHIN/EVENTOUT 21 -3600 -750 300 R 50 50 1 1 I
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X PC3/SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT 11 3400 -500 300 L 50 50 1 1 I
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X PA5/SPI1_SCK/OTG_HS_ULPI_CK/TIM2_CH1_ETR/TIM8_CHIN 21 -3600 -750 300 R 50 50 1 1 I
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X VCAP_1 31 300 -2400 300 U 50 50 1 1 I
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X PA8/MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF/EVENTOUT 41 -3600 -1050 300 R 50 50 1 1 I
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X PC10/SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/USART3_TX/EVENTOUT 51 3400 -1200 300 L 50 50 1 1 I
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X PB8/TIM4_CH3/SDIO_D4/TIM10_CH1/I2C1_SCL/CAN1_RX/EVENTOUT 61 3400 800 300 L 50 50 1 1 I
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X PA8/MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF 41 -3600 -1050 300 R 50 50 1 1 I
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X PC10/SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/USART3_TX 51 3400 -1200 300 L 50 50 1 1 I
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X PB8/TIM4_CH3/SDIO_D4/TIM10_CH1/I2C1_SCL/CAN1_RX 61 3400 800 300 L 50 50 1 1 I
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X VSSA 12 -1000 -2400 300 U 50 50 1 1 I
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X PA6/SPI1_MISO/TIM8_BKIN/TIM13_CH1/TIM3_CH1/TIM1_BKIN/EVENTOUT 22 -3600 -850 300 R 50 50 1 1 I
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X PA6/SPI1_MISO/TIM8_BKIN/TIM13_CH1/TIM3_CH1/TIM1_BKIN 22 -3600 -850 300 R 50 50 1 1 I
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X VDD 32 -100 2300 300 D 50 50 1 1 I
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X PA9/USART1_TX/TIM1_CH2/I2C3_SMBA/EVENTOUT 42 -3600 -1150 300 R 50 50 1 1 I
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X PC11/UART4_RX/SPI3_MISO/SDIO_D3/USART3_RX/I2S3ext_SD/EVENTOUT 52 3400 -1300 300 L 50 50 1 1 I
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X PB9/SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/I2C1_SDA/CAN1_TX/EVENTOUT 62 3400 700 300 L 50 50 1 1 I
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X PA9/USART1_TX/TIM1_CH2/I2C3_SMBA 42 -3600 -1150 300 R 50 50 1 1 I
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X PC11/UART4_RX/SPI3_MISO/SDIO_D3/USART3_RX/I2S3ext_SD 52 3400 -1300 300 L 50 50 1 1 I
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X PB9/SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/I2C1_SDA/CAN1_TX 62 3400 700 300 L 50 50 1 1 I
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X VDDA 13 -900 2300 300 D 50 50 1 1 I
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X PA7/SPI1_MOSI/TIM8_CH1N/TIM14_CH1/TIM3_CH2/TIM1_CH1N/EVENTOUT 23 -3600 -950 300 R 50 50 1 1 I
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X PB12/SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN/CAN2_RX/OTG_HS_ULPI_D5/OTG_HS_ID/EVENTOUT 33 3400 400 300 L 50 50 1 1 I
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X PA10/USART1_RX/TIM1_CH3/OTG_FS_ID/EVENTOUT 43 -3600 -1250 300 R 50 50 1 1 I
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X PC12/UART5_TX/SDIO_CK/SPI3_MOSI/I2S3_SD/USART3_CK/EVENTOUT 53 3400 -1400 300 L 50 50 1 1 I
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X PA7/SPI1_MOSI/TIM8_CH1N/TIM14_CH1/TIM3_CH2/TIM1_CH1N 23 -3600 -950 300 R 50 50 1 1 I
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X PB12/SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN/CAN2_RX/OTG_HS_ULPI_D5/OTG_HS_ID 33 3400 400 300 L 50 50 1 1 I
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X PA10/USART1_RX/TIM1_CH3/OTG_FS_ID 43 -3600 -1250 300 R 50 50 1 1 I
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X PC12/UART5_TX/SDIO_CK/SPI3_MOSI/I2S3_SD/USART3_CK 53 3400 -1400 300 L 50 50 1 1 I
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X VSS 63 -600 -2400 300 U 50 50 1 1 I
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X PA0/WKUP/USART2_CTS/UART4_TX/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR/EVENTOUT 14 -3600 -250 300 R 50 50 1 1 I
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X PC4/EVENTOUT 24 3400 -600 300 L 50 50 1 1 I
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X PB13/SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N/CAN2_TX/OTG_HS_ULPI_D6/EVENTOUT 34 3400 300 300 L 50 50 1 1 I
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X PA11/USART1_CTS/CAN1_RX/TIM1_CH4_/OTG_FS_DM/EVENTOUT 44 -3600 -1350 300 R 50 50 1 1 I
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X PD2/TIM3_ETR/UART5_RX/SDIO_CMD/EVENTOUT 54 -3600 150 300 R 50 50 1 1 I
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X PA0/WKUP/USART2_CTS/UART4_TX/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR 14 -3600 -250 300 R 50 50 1 1 I
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X PC4 24 3400 -600 300 L 50 50 1 1 I
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X PB13/SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N/CAN2_TX/OTG_HS_ULPI_D6 34 3400 300 300 L 50 50 1 1 I
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X PA11/USART1_CTS/CAN1_RX/TIM1_CH4_/OTG_FS_DM 44 -3600 -1350 300 R 50 50 1 1 I
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X PD2/TIM3_ETR/UART5_RX/SDIO_CMD 54 -3600 150 300 R 50 50 1 1 I
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X VDD 64 500 2300 300 D 50 50 1 1 I
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X PA1/USART2_RTS/UART4_RX/TIM5_CH2/TIMM2_CH2/EVENTOUT 15 -3600 -350 300 R 50 50 1 1 I
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X PC5/EVENTOUT 25 3400 -700 300 L 50 50 1 1 I
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X PB14/SPI2_MISO/TIM1_CH2N/TIM12_CH1/OTG_HS_DM/USART3_RTS/TIM8_CH2N/I2S2ext_SD/EVENTOUT 35 3400 200 300 L 50 50 1 1 I
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X PA12/USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP/EVENTOUT 45 -3600 -1450 300 R 50 50 1 1 I
|
||||
X PB3/JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK/EVENTOUT 55 3400 1300 300 L 50 50 1 1 I
|
||||
X PA2/USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3/EVENTOUT 16 -3600 -450 300 R 50 50 1 1 I
|
||||
X PB0/TIM3_CH3/TIM8_CH2N/OTG_HS_ULPI_D1/TIM1_CH2N/EVENTOUT 26 3400 1600 300 L 50 50 1 1 I
|
||||
X PB15/SPI2_MOSI/I2S2_SD/TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP/EVENTOUT 36 3400 100 300 L 50 50 1 1 I
|
||||
X PA13/JTMS/SWDIO/EVENTOUT 46 -3600 -1550 300 R 50 50 1 1 I
|
||||
X PB4/NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD/EVENTOUT 56 3400 1200 300 L 50 50 1 1 I
|
||||
X PA3/USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/OTG_HS_ULPI_D0/EVENTOUT 17 -3600 -550 300 R 50 50 1 1 I
|
||||
X PB1/TIM3_CH4/TIM8_CH3N/OTG_HS_ULPI_D2/OTG_HS_INTN/TIM1_CH3N/EVENTOUT 27 3400 1500 300 L 50 50 1 1 I
|
||||
X PC6/I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/TIM3_CH1/EVENTOUT 37 3400 -800 300 L 50 50 1 1 I
|
||||
X PA1/USART2_RTS/UART4_RX/TIM5_CH2/TIMM2_CH2 15 -3600 -350 300 R 50 50 1 1 I
|
||||
X PC5 25 3400 -700 300 L 50 50 1 1 I
|
||||
X PB14/SPI2_MISO/TIM1_CH2N/TIM12_CH1/OTG_HS_DM/USART3_RTS/TIM8_CH2N/I2S2ext_SD 35 3400 200 300 L 50 50 1 1 I
|
||||
X PA12/USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP 45 -3600 -1450 300 R 50 50 1 1 I
|
||||
X PB3/JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK 55 3400 1300 300 L 50 50 1 1 I
|
||||
X PA2/USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3 16 -3600 -450 300 R 50 50 1 1 I
|
||||
X PB0/TIM3_CH3/TIM8_CH2N/OTG_HS_ULPI_D1/TIM1_CH2N 26 3400 1600 300 L 50 50 1 1 I
|
||||
X PB15/SPI2_MOSI/I2S2_SD/TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP 36 3400 100 300 L 50 50 1 1 I
|
||||
X PA13/JTMS/SWDIO 46 -3600 -1550 300 R 50 50 1 1 I
|
||||
X PB4/NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD 56 3400 1200 300 L 50 50 1 1 I
|
||||
X PA3/USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/OTG_HS_ULPI_D0 17 -3600 -550 300 R 50 50 1 1 I
|
||||
X PB1/TIM3_CH4/TIM8_CH3N/OTG_HS_ULPI_D2/OTG_HS_INTN/TIM1_CH3N 27 3400 1500 300 L 50 50 1 1 I
|
||||
X PC6/I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/TIM3_CH1 37 3400 -800 300 L 50 50 1 1 I
|
||||
X VCAP_2 47 800 -2400 300 U 50 50 1 1 I
|
||||
X PB5/I2C1_SMBA/CAN2_RX/OTG_HS_ULPI_D7/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/I2S3_SD/EVENTOUT 57 3400 1100 300 L 50 50 1 1 I
|
||||
X PB5/I2C1_SMBA/CAN2_RX/OTG_HS_ULPI_D7/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/I2S3_SD 57 3400 1100 300 L 50 50 1 1 I
|
||||
X VSS 18 -800 -2400 300 U 50 50 1 1 I
|
||||
X PB2/BOOT1/EVENTOUT 28 3400 1400 300 L 50 50 1 1 I
|
||||
X PC7/I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/TIM3_CH2/EVENTOUT 38 3400 -900 300 L 50 50 1 1 I
|
||||
X PB2/BOOT1 28 3400 1400 300 L 50 50 1 1 I
|
||||
X PC7/I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/TIM3_CH2 38 3400 -900 300 L 50 50 1 1 I
|
||||
X VDD 48 200 2300 300 D 50 50 1 1 I
|
||||
X PB6/I2C1_SCL/TIM4_CH1/CAN2_TX/USART1_TX/EVENTOUT 58 3400 1000 300 L 50 50 1 1 I
|
||||
X PB6/I2C1_SCL/TIM4_CH1/CAN2_TX/USART1_TX 58 3400 1000 300 L 50 50 1 1 I
|
||||
X VDD 19 -400 2300 300 D 50 50 1 1 I
|
||||
X PB10/SPI2_SCK/I2S2_CK/I2C2_SCL/USART3_TX/OTG_HS_ULPI_D3/TIM2_CH3/EVENTOUT 29 3400 600 300 L 50 50 1 1 I
|
||||
X PC8/TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK/EVENTOUT 39 3400 -1000 300 L 50 50 1 1 I
|
||||
X PA14/JTCK/SWCLK/EVENTOUT 49 -3600 -1650 300 R 50 50 1 1 I
|
||||
X PB7/I2C1_SDA/FSMC_NL/USART1_RX/TIM4_CH2/EVENTOUT 59 3400 900 300 L 50 50 1 1 I
|
||||
X PB10/SPI2_SCK/I2S2_CK/I2C2_SCL/USART3_TX/OTG_HS_ULPI_D3/TIM2_CH3 29 3400 600 300 L 50 50 1 1 I
|
||||
X PC8/TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK 39 3400 -1000 300 L 50 50 1 1 I
|
||||
X PA14/JTCK/SWCLK 49 -3600 -1650 300 R 50 50 1 1 I
|
||||
X PB7/I2C1_SDA/FSMC_NL/USART1_RX/TIM4_CH2 59 3400 900 300 L 50 50 1 1 I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
|
|
@ -1724,7 +1724,7 @@ DEF STM32F405VG U 0 40 Y Y 1 F N
|
|||
F0 "U" 0 0 60 H V C CNN
|
||||
F1 "STM32F405VG" 0 100 60 H V C CNN
|
||||
F2 "TQFP100" 0 -100 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
F3 "~" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
S -4700 -2700 4700 2700 0 1 0 f
|
||||
X PE2/TRACECLK/FSMC_A23/EVENTOUT 1 5000 2350 300 L 50 50 1 1 I
|
||||
|
|
@ -1830,13 +1830,92 @@ X VDD 100 750 3000 300 D 50 50 1 1 I
|
|||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# STM32F407R
|
||||
#
|
||||
DEF STM32F407R U 0 40 Y Y 1 F N
|
||||
F0 "U" 150 -600 60 H V C CNN
|
||||
F1 "STM32F407R" 150 -500 60 H V C CNN
|
||||
F2 "TQFP64" 150 -700 60 H V C CNN
|
||||
F3 "~" 150 -600 60 H V C CNN
|
||||
$FPLIST
|
||||
LQFP64
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -3300 -2100 3100 2000 0 1 0 f
|
||||
X VBAT 1 1000 2300 300 D 50 50 1 1 I
|
||||
X PC13 2 3400 -1500 300 L 50 50 1 1 I
|
||||
X PC14/OSC32_IN 3 3400 -1600 300 L 50 50 1 1 I
|
||||
X PC15/OSC32_OUT 4 3400 -1700 300 L 50 50 1 1 I
|
||||
X PH0/OSC_IN 5 -3600 1150 300 R 50 50 1 1 I
|
||||
X PH1/OSC_OUT 6 -3600 550 300 R 50 50 1 1 I
|
||||
X NRST 7 -3600 1350 300 R 50 50 1 1 I
|
||||
X PC0/OTG_HS_ULPI_STP 8 3400 -200 300 L 50 50 1 1 I
|
||||
X PC1/ETH_MDC/_EVENTOUT 9 3400 -300 300 L 50 50 1 1 I
|
||||
X PC2/SPI2_MISO/OTG_HS_ULPI_DIR/ETH_MII_TXD2/I2S2ext_SD 10 3400 -400 300 L 50 50 1 1 I
|
||||
X PA4/SPI1_NSS/SPI3_NSS/USART2_CK/DCMI_HSYNC/OTG_HS_SOF/I2S3_WS 20 -3600 -650 300 R 50 50 1 1 I
|
||||
X PB11/I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4/ETH_RMII_TX_EN/ETH_MII_TX_EN/TIM2_CH4 30 3400 500 300 L 50 50 1 1 I
|
||||
X PC9/I2S_CKIN/MCO2/TIM8_CH4/SDIO_D1/I2C3_SDA/DCMI_D3/TIM3_CH4 40 3400 -1100 300 L 50 50 1 1 I
|
||||
X PA15/JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS 50 -3600 -1750 300 R 50 50 1 1 I
|
||||
X BOOT0 60 -3600 1550 300 R 50 50 1 1 I
|
||||
X PC3/SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT/ETH_MII_TX_CLK 11 3400 -500 300 L 50 50 1 1 I
|
||||
X PA5/SPI1_SCK/OTG_HS_ULPI_CK/TIM2_CH1_ETR/TIM8_CHIN 21 -3600 -750 300 R 50 50 1 1 I
|
||||
X VCAP_1 31 300 -2400 300 U 50 50 1 1 I
|
||||
X PA8/MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF 41 -3600 -1050 300 R 50 50 1 1 I
|
||||
X PC10/SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/DCMI_D8/USART3_TX 51 3400 -1200 300 L 50 50 1 1 I
|
||||
X PB8/TIM4_CH3/SDIO_D4/TIM10_CH1/DCMI_D6/ETH_MII_TXD3/I2C1_SCL/CAN1_RX 61 3400 800 300 L 50 50 1 1 I
|
||||
X VSSA 12 -1000 -2400 300 U 50 50 1 1 I
|
||||
X PA6/SPI1_MISO/TIM8_BKIN/TIM13_CH1/DCMI_PIXCLK/TIM3_CH1/TIM1_BKIN 22 -3600 -850 300 R 50 50 1 1 I
|
||||
X VDD 32 -100 2300 300 D 50 50 1 1 I
|
||||
X PA9/USART1_TX/TIM1_CH2/I2C3_SMBA/DCMI_D0 42 -3600 -1150 300 R 50 50 1 1 I
|
||||
X PC11/UART4_RX/SPI3_MISO/SDIO_D3/DCMI_D4/USART3_RX/I2S3ext_SD 52 3400 -1300 300 L 50 50 1 1 I
|
||||
X PB9/SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/DCMI_D7/I2C1_SDA/CAN1_TX 62 3400 700 300 L 50 50 1 1 I
|
||||
X VDDA 13 -900 2300 300 D 50 50 1 1 I
|
||||
X PA7/SPI1_MOSI/TIM8_CH1N/TIM14_CH1/TIM3_CH2/ETH_MII_RX_DV/TIM1_CH1N/RMII_CRS_DV 23 -3600 -950 300 R 50 50 1 1 I
|
||||
X PB12/SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN/CAN2_RX/OTG_HS_ULPI_D5/ETH_RMII_TXD0/ETH_MII_TXD0/OTG_HS_ID 33 3400 400 300 L 50 50 1 1 I
|
||||
X PA10/USART1_RX/TIM1_CH3/OTG_FS_ID/DCMI_D1 43 -3600 -1250 300 R 50 50 1 1 I
|
||||
X PC12/UART5_TX/SDIO_CK/DCMI_D9/SPI3_MOSI/I2S3_SD/USART3_CK 53 3400 -1400 300 L 50 50 1 1 I
|
||||
X VSS 63 -600 -2400 300 U 50 50 1 1 I
|
||||
X PA0/WKUP/USART2_CTS/UART4_TX/ETH_MII_CRS_/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR 14 -3600 -250 300 R 50 50 1 1 I
|
||||
X PC4/ETH_RMII_RX_D0/ETH_MII_RX_D0 24 3400 -600 300 L 50 50 1 1 I
|
||||
X PB13/SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N/CAN2_TX/OTG_HS_ULPI_D6/ETH_RMII_TXD1/ETH_MII_TXD1 34 3400 300 300 L 50 50 1 1 I
|
||||
X PA11/USART1_CTS/CAN1_RX/TIM1_CH4_/OTG_FS_DM 44 -3600 -1350 300 R 50 50 1 1 I
|
||||
X PD2/TIM3_ETR/UART5_RX/SDIO_CMD/DCMI_D11 54 -3600 150 300 R 50 50 1 1 I
|
||||
X VDD 64 500 2300 300 D 50 50 1 1 I
|
||||
X PA1/USART2_RTS/UART4_RX/ETH_RMII_REF_CLK/ETH_MII_RX_CLK/TIM5_CH2/TIMM2_CH2 15 -3600 -350 300 R 50 50 1 1 I
|
||||
X PC5/ETH_RMII_RX_D1/ETH_MII_RX_D1 25 3400 -700 300 L 50 50 1 1 I
|
||||
X PB14/SPI2_MISO/TIM1_CH2N/TIM12_CH1/OTG_HS_DM/USART3_RTS/TIM8_CH2N/I2S2ext_SD 35 3400 200 300 L 50 50 1 1 I
|
||||
X PA12/USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP 45 -3600 -1450 300 R 50 50 1 1 I
|
||||
X PB3/JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK 55 3400 1300 300 L 50 50 1 1 I
|
||||
X PA2/USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3/ETH_MDIO 16 -3600 -450 300 R 50 50 1 1 I
|
||||
X PB0/TIM3_CH3/TIM8_CH2N/OTG_HS_ULPI_D1/ETH_MII_RXD2/TIM1_CH2N 26 3400 1600 300 L 50 50 1 1 I
|
||||
X PB15/SPI2_MOSI/I2S2_SD/TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP 36 3400 100 300 L 50 50 1 1 I
|
||||
X PA13/JTMS/SWDIO 46 -3600 -1550 300 R 50 50 1 1 I
|
||||
X PB4/NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD 56 3400 1200 300 L 50 50 1 1 I
|
||||
X PA3/USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/OTG_HS_ULPI_D0/ETH_MII_COL 17 -3600 -550 300 R 50 50 1 1 I
|
||||
X PB1/TIM3_CH4/TIM8_CH3N/OTG_HS_ULPI_D2/ETH_MII_RXD3/OTG_HS_INTN/TIM1_CH3N 27 3400 1500 300 L 50 50 1 1 I
|
||||
X PC6/I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/DCMI_D0/TIM3_CH1 37 3400 -800 300 L 50 50 1 1 I
|
||||
X VCAP_2 47 800 -2400 300 U 50 50 1 1 I
|
||||
X PB5/I2C1_SMBA/CAN2_RX/OTG_HS_ULPI_D7/ETH_PPS_OUT/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/DCMI_D10/I2S3_SD 57 3400 1100 300 L 50 50 1 1 I
|
||||
X VSS 18 -800 -2400 300 U 50 50 1 1 I
|
||||
X PB2/BOOT1 28 3400 1400 300 L 50 50 1 1 I
|
||||
X PC7/I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/DCMI_D1/TIM3_CH2 38 3400 -900 300 L 50 50 1 1 I
|
||||
X VDD 48 200 2300 300 D 50 50 1 1 I
|
||||
X PB6/I2C1_SCL/TIM4_CH1/CAN2_TX/DCMI_D5/USART1_TX 58 3400 1000 300 L 50 50 1 1 I
|
||||
X VDD 19 -400 2300 300 D 50 50 1 1 I
|
||||
X PB10/SPI2_SCK/I2S2_CK/I2C2_SCL/USART3_TX/OTG_HS_ULPI_D3/ETH_MII_RX_ER/TIM2_CH3 29 3400 600 300 L 50 50 1 1 I
|
||||
X PC8/TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK/DCMI_D2 39 3400 -1000 300 L 50 50 1 1 I
|
||||
X PA14/JTCK/SWCLK 49 -3600 -1650 300 R 50 50 1 1 I
|
||||
X PB7/I2C1_SDA/FSMC_NL/DCMI_VSYNC/USART1_RX/TIM4_CH2 59 3400 900 300 L 50 50 1 1 I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# STM32F407VE
|
||||
#
|
||||
DEF STM32F407VE U 0 40 Y Y 1 F N
|
||||
F0 "U" 0 0 60 H V C CNN
|
||||
F1 "STM32F407VE" 0 100 60 H V C CNN
|
||||
F2 "TQFP100" 0 -100 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
F3 "~" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
S -4700 -2700 4700 2700 0 1 0 f
|
||||
X PE2/TRACECLK/FSMC_A23/ETH_MII_TXD3/EVENTOUT 1 5000 2350 300 L 50 50 1 1 I
|
||||
|
|
@ -1948,7 +2027,7 @@ DEF STM32F407VG U 0 40 Y Y 1 F N
|
|||
F0 "U" 0 0 60 H V C CNN
|
||||
F1 "STM32F407VG" 0 100 60 H V C CNN
|
||||
F2 "TQFP100" 0 -100 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
F3 "~" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
S -4700 -2700 4700 2700 0 1 0 f
|
||||
X PE2/TRACECLK/FSMC_A23/ETH_MII_TXD3/EVENTOUT 1 5000 2350 300 L 50 50 1 1 I
|
||||
|
|
@ -2060,7 +2139,7 @@ DEF STM32F415VG U 0 40 Y Y 1 F N
|
|||
F0 "U" 0 0 60 H V C CNN
|
||||
F1 "STM32F415VG" 0 100 60 H V C CNN
|
||||
F2 "TQFP100" 0 -100 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
F3 "~" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
S -4700 -2700 4700 2700 0 1 0 f
|
||||
X PE2/TRACECLK/FSMC_A23/EVENTOUT 1 5000 2350 300 L 50 50 1 1 I
|
||||
|
|
@ -2172,7 +2251,7 @@ DEF STM32F417VE U 0 40 Y Y 1 F N
|
|||
F0 "U" 0 0 60 H V C CNN
|
||||
F1 "STM32F417VE" 0 100 60 H V C CNN
|
||||
F2 "TQFP100" 0 -100 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
F3 "~" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
S -4700 -2700 4700 2700 0 1 0 f
|
||||
X PE2/TRACECLK/FSMC_A23/ETH_MII_TXD3/EVENTOUT 1 5000 2350 300 L 50 50 1 1 I
|
||||
|
|
@ -2284,7 +2363,7 @@ DEF STM32F417VG U 0 40 Y Y 1 F N
|
|||
F0 "U" 0 0 60 H V C CNN
|
||||
F1 "STM32F417VG" 0 100 60 H V C CNN
|
||||
F2 "TQFP100" 0 -100 60 H V C CNN
|
||||
F3 "" 0 0 60 H V C CNN
|
||||
F3 "~" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
S -4700 -2700 4700 2700 0 1 0 f
|
||||
X PE2/TRACECLK/FSMC_A23/ETH_MII_TXD3/EVENTOUT 1 5000 2350 300 L 50 50 1 1 I
|
||||
|
|
|
|||
Loading…
Reference in a new issue