Add EuroCard 160mm x 100mm outlines with and without holes.
This commit is contained in:
David Griffith
parent
2aa55c1330
commit
dfdc11bb3d
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@ -14,6 +14,8 @@ set( template_lst
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ti-stellaris-boosterpack40_min
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BeagleBone-Black-Cape
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minnowboard-ls-lure
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EuroCard160mmX100mm
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EuroCard160mmX100mm_holes
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)
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@ -0,0 +1,106 @@
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(kicad_pcb (version 20170123) (host pcbnew "(2017-07-16 revision e797af331)-master")
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(general
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(thickness 1.6)
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(drawings 4)
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(tracks 0)
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(zones 0)
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(modules 0)
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(nets 1)
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)
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(page A4)
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(layers
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(0 F.Cu signal)
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(31 B.Cu signal)
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(32 B.Adhes user)
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(33 F.Adhes user)
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(34 B.Paste user)
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(35 F.Paste user)
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(36 B.SilkS user)
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(37 F.SilkS user)
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(38 B.Mask user)
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(39 F.Mask user)
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(40 Dwgs.User user)
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(41 Cmts.User user)
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(42 Eco1.User user)
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(43 Eco2.User user)
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(44 Edge.Cuts user)
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(45 Margin user)
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(46 B.CrtYd user)
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(47 F.CrtYd user)
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(48 B.Fab user)
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(49 F.Fab user)
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)
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(setup
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(last_trace_width 0.25)
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(trace_clearance 0.2)
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(zone_clearance 0.508)
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||||
(zone_45_only no)
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(trace_min 0.2)
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(segment_width 0.2)
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(edge_width 0.15)
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(via_size 0.8)
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(via_drill 0.4)
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(via_min_size 0.4)
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(via_min_drill 0.3)
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(uvia_size 0.3)
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(uvia_drill 0.1)
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(uvias_allowed no)
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(uvia_min_size 0.2)
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(uvia_min_drill 0.1)
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(pcb_text_width 0.3)
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||||
(pcb_text_size 1.5 1.5)
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||||
(mod_edge_width 0.15)
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(mod_text_size 1 1)
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||||
(mod_text_width 0.15)
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||||
(pad_size 1.524 1.524)
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(pad_drill 0.762)
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(pad_to_mask_clearance 0.2)
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(aux_axis_origin 0 0)
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(grid_origin 55 145)
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(visible_elements FFFFFF7F)
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||||
(pcbplotparams
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(layerselection 0x00030_ffffffff)
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||||
(usegerberextensions false)
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||||
(excludeedgelayer true)
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||||
(linewidth 0.100000)
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||||
(plotframeref false)
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(viasonmask false)
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(mode 1)
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(useauxorigin false)
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(hpglpennumber 1)
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(hpglpenspeed 20)
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(hpglpendiameter 15)
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||||
(psnegative false)
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||||
(psa4output false)
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||||
(plotreference true)
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||||
(plotvalue true)
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||||
(plotinvisibletext false)
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(padsonsilk false)
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(subtractmaskfromsilk false)
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||||
(outputformat 1)
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(mirror false)
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||||
(drillshape 0)
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(scaleselection 1)
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(outputdirectory ""))
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)
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(net 0 "")
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(net_class Default "This is the default net class."
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(clearance 0.2)
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(trace_width 0.25)
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(via_dia 0.8)
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(via_drill 0.4)
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(uvia_dia 0.3)
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(uvia_drill 0.1)
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)
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(gr_line (start 55 145) (end 215 145) (angle 90) (layer Edge.Cuts) (width 0.15))
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(gr_line (start 55 45) (end 55 145) (angle 90) (layer Edge.Cuts) (width 0.15))
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(gr_line (start 215 45) (end 55 45) (angle 90) (layer Edge.Cuts) (width 0.15))
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(gr_line (start 215 145) (end 215 45) (angle 90) (layer Edge.Cuts) (width 0.15))
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)
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@ -0,0 +1,60 @@
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update=Sun 23 Jul 2017 01:54:40 PM PDT
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version=1
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last_client=kicad
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[pcbnew]
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version=1
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LastNetListRead=
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UseCmpFile=1
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PadDrill=0.600000000000
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PadDrillOvalY=0.600000000000
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PadSizeH=1.500000000000
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PadSizeV=1.500000000000
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PcbTextSizeV=1.500000000000
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PcbTextSizeH=1.500000000000
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PcbTextThickness=0.300000000000
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ModuleTextSizeV=1.000000000000
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ModuleTextSizeH=1.000000000000
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ModuleTextSizeThickness=0.150000000000
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SolderMaskClearance=0.000000000000
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SolderMaskMinWidth=0.000000000000
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DrawSegmentWidth=0.200000000000
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BoardOutlineThickness=0.100000000000
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ModuleOutlineThickness=0.150000000000
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[cvpcb]
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version=1
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NetIExt=net
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[eeschema]
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version=1
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LibDir=
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[eeschema/libraries]
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LibName1=power
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LibName2=device
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LibName3=transistors
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LibName4=conn
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LibName5=linear
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LibName6=regul
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LibName7=74xx
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LibName8=cmos4000
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LibName9=adc-dac
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LibName10=memory
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LibName11=xilinx
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LibName12=microcontrollers
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LibName13=dsp
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LibName14=microchip
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LibName15=analog_switches
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LibName16=motorola
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LibName17=texas
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LibName18=intel
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LibName19=audio
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LibName20=interface
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LibName21=digital-audio
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LibName22=philips
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LibName23=display
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LibName24=cypress
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LibName25=siliconi
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LibName26=opto
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LibName27=atmel
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LibName28=contrib
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LibName29=valves
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[general]
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version=1
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@ -0,0 +1,4 @@
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EESchema Schematic File Version 2
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EELAYER 25 0
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EELAYER END
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$EndSCHEMATC
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Binary file not shown.
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After Width: | Height: | Size: 11 KiB |
Binary file not shown.
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After Width: | Height: | Size: 1.7 KiB |
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@ -0,0 +1,21 @@
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<html>
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<head>
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<META HTTP-EQUIV="CONTENT-TYPE" CONTENT="text/html; charset=utf-8">
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<title>EuroCard 160mm x 100mm</title>
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</head>
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<body>
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<p>
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This project template provides the outline of a standard 3U
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<a href="https://en.wikipedia.org/wiki/Eurocard_(printed_circuit_board)" TARGET="blank">EuroCard</a>
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measuring 160mm by 100mm.
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The final PCB looks like the following:
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<p>
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<p><img src="brd.png" name="brd" ALIGN=BOTTOM WIDTH=600 HEIGHT=390
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BORDER=0><BR><BR><BR><BR>
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</p>
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<p>(c)2017 David Griffith<br></p>
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</body>
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</html>
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@ -0,0 +1,166 @@
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(kicad_pcb (version 20170123) (host pcbnew "(2017-07-16 revision e797af331)-master")
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(general
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(thickness 1.6)
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(drawings 4)
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(tracks 0)
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(zones 0)
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(modules 4)
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(nets 1)
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)
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(page A4)
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(layers
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(0 F.Cu signal)
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(31 B.Cu signal)
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(32 B.Adhes user)
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(33 F.Adhes user)
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(34 B.Paste user)
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(35 F.Paste user)
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(36 B.SilkS user)
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(37 F.SilkS user)
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(38 B.Mask user)
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(39 F.Mask user)
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(40 Dwgs.User user)
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(41 Cmts.User user)
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(42 Eco1.User user)
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(43 Eco2.User user)
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(44 Edge.Cuts user)
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(45 Margin user)
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(46 B.CrtYd user)
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(47 F.CrtYd user)
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(48 B.Fab user)
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(49 F.Fab user)
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)
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(setup
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(last_trace_width 0.25)
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(trace_clearance 0.2)
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(zone_clearance 0.508)
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||||
(zone_45_only no)
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||||
(trace_min 0.2)
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||||
(segment_width 0.2)
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||||
(edge_width 0.15)
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||||
(via_size 0.8)
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(via_drill 0.4)
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||||
(via_min_size 0.4)
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(via_min_drill 0.3)
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(uvia_size 0.3)
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||||
(uvia_drill 0.1)
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||||
(uvias_allowed no)
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(uvia_min_size 0.2)
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||||
(uvia_min_drill 0.1)
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||||
(pcb_text_width 0.3)
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||||
(pcb_text_size 1.5 1.5)
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||||
(mod_edge_width 0.15)
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||||
(mod_text_size 1 1)
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||||
(mod_text_width 0.15)
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||||
(pad_size 1.524 1.524)
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||||
(pad_drill 0.762)
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||||
(pad_to_mask_clearance 0.2)
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||||
(aux_axis_origin 0 0)
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||||
(grid_origin 55 145)
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||||
(visible_elements FFFFFF7F)
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||||
(pcbplotparams
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||||
(layerselection 0x00030_ffffffff)
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||||
(usegerberextensions false)
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||||
(excludeedgelayer true)
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||||
(linewidth 0.100000)
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||||
(plotframeref false)
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||||
(viasonmask false)
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(mode 1)
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||||
(useauxorigin false)
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||||
(hpglpennumber 1)
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(hpglpenspeed 20)
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||||
(hpglpendiameter 15)
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||||
(psnegative false)
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||||
(psa4output false)
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||||
(plotreference true)
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||||
(plotvalue true)
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||||
(plotinvisibletext false)
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||||
(padsonsilk false)
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(subtractmaskfromsilk false)
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||||
(outputformat 1)
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||||
(mirror false)
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||||
(drillshape 0)
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||||
(scaleselection 1)
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||||
(outputdirectory ""))
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||||
)
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||||
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||||
(net 0 "")
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||||
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||||
(net_class Default "This is the default net class."
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||||
(clearance 0.2)
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||||
(trace_width 0.25)
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||||
(via_dia 0.8)
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(via_drill 0.4)
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(uvia_dia 0.3)
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(uvia_drill 0.1)
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)
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(module Mounting_Holes:MountingHole_3.5mm (layer F.Cu) (tedit 59754677) (tstamp 59755F5D)
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(at 211.43 139.45)
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(descr "Mounting Hole 3.5mm, no annular")
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(tags "mounting hole 3.5mm no annular")
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(fp_text reference REF** (at 0 -4.5) (layer F.SilkS) hide
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_text value MountingHole_3.5mm (at 0 4.5) (layer F.Fab) hide
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_circle (center 0 0) (end 3.75 0) (layer F.CrtYd) (width 0.05))
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(fp_circle (center 0 0) (end 3.5 0) (layer Cmts.User) (width 0.15))
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(pad 1 np_thru_hole circle (at 0 0) (size 3.5 3.5) (drill 3.5) (layers *.Cu *.Mask))
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)
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(module Mounting_Holes:MountingHole_3.5mm (layer F.Cu) (tedit 59754677) (tstamp 59755F56)
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(at 211.43 50.55)
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(descr "Mounting Hole 3.5mm, no annular")
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(tags "mounting hole 3.5mm no annular")
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(fp_text reference REF** (at 0 -4.5) (layer F.SilkS) hide
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_text value MountingHole_3.5mm (at 0 4.5) (layer F.Fab) hide
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_circle (center 0 0) (end 3.5 0) (layer Cmts.User) (width 0.15))
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(fp_circle (center 0 0) (end 3.75 0) (layer F.CrtYd) (width 0.05))
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(pad 1 np_thru_hole circle (at 0 0) (size 3.5 3.5) (drill 3.5) (layers *.Cu *.Mask))
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)
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(module Mounting_Holes:MountingHole_3.5mm (layer F.Cu) (tedit 59754677) (tstamp 59755B13)
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(at 58.57 50.55)
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(descr "Mounting Hole 3.5mm, no annular")
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(tags "mounting hole 3.5mm no annular")
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(fp_text reference REF** (at 0 -4.5) (layer F.SilkS) hide
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_text value MountingHole_3.5mm (at 0 4.5) (layer F.Fab) hide
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_circle (center 0 0) (end 3.75 0) (layer F.CrtYd) (width 0.05))
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(fp_circle (center 0 0) (end 3.5 0) (layer Cmts.User) (width 0.15))
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(pad 1 np_thru_hole circle (at 0 0) (size 3.5 3.5) (drill 3.5) (layers *.Cu *.Mask))
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)
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(module Mounting_Holes:MountingHole_3.5mm (layer F.Cu) (tedit 59754677) (tstamp 597559B3)
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(at 58.57 139.45)
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(descr "Mounting Hole 3.5mm, no annular")
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(tags "mounting hole 3.5mm no annular")
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(fp_text reference REF** (at 0 -4.5) (layer F.SilkS) hide
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_text value MountingHole_3.5mm (at 0 4.5) (layer F.Fab) hide
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_circle (center 0 0) (end 3.5 0) (layer Cmts.User) (width 0.15))
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(fp_circle (center 0 0) (end 3.75 0) (layer F.CrtYd) (width 0.05))
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(pad 1 np_thru_hole circle (at 0 0) (size 3.5 3.5) (drill 3.5) (layers *.Cu *.Mask))
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)
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(gr_line (start 55 145) (end 215 145) (angle 90) (layer Edge.Cuts) (width 0.15))
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(gr_line (start 55 45) (end 55 145) (angle 90) (layer Edge.Cuts) (width 0.15))
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(gr_line (start 215 45) (end 55 45) (angle 90) (layer Edge.Cuts) (width 0.15))
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(gr_line (start 215 145) (end 215 45) (angle 90) (layer Edge.Cuts) (width 0.15))
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)
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@ -0,0 +1,60 @@
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update=Sun 23 Jul 2017 05:55:46 PM PDT
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version=1
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last_client=kicad
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[pcbnew]
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version=1
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LastNetListRead=
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UseCmpFile=1
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PadDrill=0.600000000000
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PadDrillOvalY=0.600000000000
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PadSizeH=1.500000000000
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PadSizeV=1.500000000000
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PcbTextSizeV=1.500000000000
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PcbTextSizeH=1.500000000000
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PcbTextThickness=0.300000000000
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ModuleTextSizeV=1.000000000000
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ModuleTextSizeH=1.000000000000
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ModuleTextSizeThickness=0.150000000000
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SolderMaskClearance=0.000000000000
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SolderMaskMinWidth=0.000000000000
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DrawSegmentWidth=0.200000000000
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BoardOutlineThickness=0.100000000000
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ModuleOutlineThickness=0.150000000000
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[cvpcb]
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version=1
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NetIExt=net
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[eeschema]
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version=1
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||||
LibDir=
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[eeschema/libraries]
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LibName1=power
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LibName2=device
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LibName3=transistors
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LibName4=conn
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LibName5=linear
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LibName6=regul
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LibName7=74xx
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LibName8=cmos4000
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LibName9=adc-dac
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LibName10=memory
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LibName11=xilinx
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LibName12=microcontrollers
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LibName13=dsp
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LibName14=microchip
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LibName15=analog_switches
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LibName16=motorola
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LibName17=texas
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LibName18=intel
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LibName19=audio
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LibName20=interface
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LibName21=digital-audio
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LibName22=philips
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LibName23=display
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LibName24=cypress
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LibName25=siliconi
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LibName26=opto
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LibName27=atmel
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LibName28=contrib
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LibName29=valves
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[general]
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version=1
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||||
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@ -0,0 +1,4 @@
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EESchema Schematic File Version 2
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||||
EELAYER 25 0
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||||
EELAYER END
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||||
$EndSCHEMATC
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||||
Binary file not shown.
|
After Width: | Height: | Size: 33 KiB |
Binary file not shown.
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After Width: | Height: | Size: 2.1 KiB |
|
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@ -0,0 +1,21 @@
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|||
<html>
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||||
<head>
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||||
<META HTTP-EQUIV="CONTENT-TYPE" CONTENT="text/html; charset=utf-8">
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||||
<title>EuroCard 160mm x 100mm with holes</title>
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||||
</head>
|
||||
<body>
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||||
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||||
<p>
|
||||
This project template provides the outline of a standard 3U
|
||||
<a href="https://en.wikipedia.org/wiki/Eurocard_(printed_circuit_board)" TARGET="blank">EuroCard</a>
|
||||
measuring 160mm by 100mm with mounting holes.
|
||||
|
||||
The final PCB looks like the following:
|
||||
<p>
|
||||
<p><img src="brd.png" name="brd" ALIGN=BOTTOM WIDTH=600 HEIGHT=390
|
||||
BORDER=0><BR><BR><BR><BR>
|
||||
</p>
|
||||
|
||||
<p>(c)2017 David Griffith<br></p>
|
||||
</body>
|
||||
</html>
|
||||
Loading…
Reference in New Issue