Update CS8420 for HW and SW modes

This commit is contained in:
evanshultz 2017-07-20 19:14:53 -07:00 committed by GitHub
parent 5d324b151f
commit dbd9400cb1

View file

@ -442,43 +442,46 @@ X C/GPO1 19 900 -300 150 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# CS8420_SOFT
# CS8420
#
DEF CS8420_SOFT U 0 40 Y Y 1 F N
F0 "U" 50 250 50 H V C CNN
F1 "CS8420_SOFT" 50 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
DEF CS8420 U 0 10 Y Y 1 F N
F0 "U" 450 1200 50 H V C CNN
F1 "CS8420" 450 1100 50 H V C CNN
F2 "Housings_SOIC:SOIC-28W_7.5x17.9mm_Pitch1.27mm" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
SOIC*7.5x17.9mm*Pitch1.27mm*
$ENDFPLIST
DRAW
S -650 950 650 -950 0 1 0 f
X SDA/CDOUT 1 -800 0 150 R 50 50 1 1 B
X AD0/CS- 2 -800 -200 150 R 50 50 1 1 I
X EMPH-/AD2 3 800 -600 150 L 50 50 1 1 O
X RXP 4 -800 400 150 R 50 50 1 1 I
X RXN 5 -800 300 150 R 50 50 1 1 I
X VA 6 -100 1100 150 D 50 50 1 1 I
X AGND 7 -100 -1100 150 U 50 50 1 1 I
X FILT 8 -800 -800 150 R 50 50 1 1 I
X RST 9 -800 -600 150 R 50 50 1 1 I
X RMCK 10 800 400 150 L 50 50 1 1 B
X U 20 800 -300 150 L 50 50 1 1 B
X RERR 11 800 -500 150 L 50 50 1 1 O
X OMCK 21 800 300 150 L 50 50 1 1 I
X ILRCK 12 -800 800 150 R 50 50 1 1 B
X DGND 22 100 -1100 150 U 50 50 1 1 I
X ISCLK 13 -800 700 150 R 50 50 1 1 B
X VD 23 100 1100 150 D 50 50 1 1 I
X SDIN 14 -800 600 150 R 50 50 1 1 I
X H/S- 24 -800 -500 150 R 50 50 1 1 I
X TCBL 15 800 -100 150 L 50 50 1 1 B
X TXN 25 800 0 150 L 50 50 1 1 O
X OSCLK 16 800 700 150 L 50 50 1 1 B
X TXP 26 800 100 150 L 50 50 1 1 O
X OLRCK 17 800 800 150 L 50 50 1 1 B
X AD1/CDIN 27 -800 -300 150 R 50 50 1 1 I
X SDOUT 18 800 600 150 L 50 50 1 1 O
X SCL/CCLK 28 -800 -100 150 R 50 50 1 1 B
X INT 19 800 -800 150 L 50 50 1 1 C
S -750 1050 750 -1050 0 1 10 f
X SDA/CDOUT/COPY/C 1 -900 0 150 R 50 50 1 1 B
X AD0/~CS~/DFC0 2 -900 -200 150 R 50 50 1 1 I
X ~EMPH~/U/V 3 900 -600 150 L 50 50 1 1 B
X RXP/SMFT0 4 -900 400 150 R 50 50 1 1 I
X RXN/SMFT1 5 -900 300 150 R 50 50 1 1 I
X VA+ 6 -100 1200 150 D 50 50 1 1 W
X AGND 7 -100 -1200 150 U 50 50 1 1 W
X FILT 8 -900 -800 150 R 50 50 1 1 P
X ~RST 9 -900 -600 150 R 50 50 1 1 I
X RMCK/APMS 10 900 400 150 L 50 50 1 1 B
X RERR/~LOCK~/TBCLD 11 900 -500 150 L 50 50 1 1 O
X ILRCK/TCBLD/RCBL 12 -900 800 150 R 50 50 1 1 B
X ISCLK/PRO/C 13 -900 700 150 R 50 50 1 1 B
X SDIN/MUTE/CHS 14 -900 600 150 R 50 50 1 1 I
X TCBL/NVERR 15 900 -100 150 L 50 50 1 1 B
X OSCLK/CEN 16 900 700 150 L 50 50 1 1 B
X OLRCK/V 17 900 800 150 L 50 50 1 1 B
X SDOUT/U 18 900 600 150 L 50 50 1 1 B
X INT/~AUDIO~/V/CUVEN 19 900 -800 150 L 50 50 1 1 B
X U/S/~AES~/PRO/C 20 900 -300 150 L 50 50 1 1 B
X OMCK/APMS 21 900 300 150 L 50 50 1 1 I
X DGND 22 100 -1200 150 U 50 50 1 1 W
X VD+ 23 100 1200 150 D 50 50 1 1 W
X H/~S 24 -900 -500 150 R 50 50 1 1 I
X TXN/U 25 900 0 150 L 50 50 1 1 O
X TXP/C 26 900 100 150 L 50 50 1 1 O
X AD1/CDIN/DFC1 27 -900 -300 150 R 50 50 1 1 I
X SCL/CCLK/ORIG/U 28 -900 -100 150 R 50 50 1 1 B
ENDDRAW
ENDDEF
#