Deleted symbols to be replaced by aliases.
This commit is contained in:
hackscribble
parent
614491629f
commit
d72e9b0a14
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@ -408,36 +408,6 @@ K ARM, 32bit, CortexM3, M3, NXP, Microcontroller
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F http://www.nxp.com/documents/data_sheet/LPC1769_68_67_66_65_64_63.pdf
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$ENDCMP
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#
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$CMP LPC1764FBD100
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D LPC1769, 32-bit ARM Cortex-M3 microcontroller, 128 kB Flash, 32 kB SRAM, Ethernet, USB 2.0 Device, CAN
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K ARM, 32bit, CortexM3, M3, NXP, Microcontroller
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F http://www.nxp.com/documents/data_sheet/LPC1769_68_67_66_65_64_63.pdf
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$ENDCMP
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#
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$CMP LPC1765FBD100
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D LPC1769, 32-bit ARM Cortex-M3 microcontroller, 256 kB Flash, 64 kB SRAM, USB 2.0 Host/Device/OTG, CAN, I2S, DAC
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K ARM, 32bit, CortexM3, M3, NXP, Microcontroller
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F http://www.nxp.com/documents/data_sheet/LPC1769_68_67_66_65_64_63.pdf
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$ENDCMP
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#
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$CMP LPC1766FBD100
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D LPC1769, 32-bit ARM Cortex-M3 microcontroller, 256 kB Flash, 64 kB SRAM, Ethernet, USB 2.0 Host/Device/OTG, CAN, I2S, DAC
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K ARM, 32bit, CortexM3, M3, NXP, Microcontroller
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F http://www.nxp.com/documents/data_sheet/LPC1769_68_67_66_65_64_63.pdf
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$ENDCMP
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#
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$CMP LPC1767FBD100
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D LPC1769, 32-bit ARM Cortex-M3 microcontroller, 512 kB Flash, 64 kB SRAM, Ethernet, I2S, DAC
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K ARM, 32bit, CortexM3, M3, NXP, Microcontroller
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F http://www.nxp.com/documents/data_sheet/LPC1769_68_67_66_65_64_63.pdf
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$ENDCMP
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#
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$CMP LPC1769FBD100
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D LPC1769, 32-bit ARM Cortex-M3 microcontroller, 512 kB Flash, 64 kB SRAM, Ethernet, USB 2.0 Host/Device/OTG, CAN, I2S, DAC
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K ARM, 32bit, CortexM3, M3, NXP, Microcontroller
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F http://www.nxp.com/documents/data_sheet/LPC1769_68_67_66_65_64_63.pdf
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$ENDCMP
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#
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$CMP LPC812M101JD20
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D LPC81xM, 30MHz Cortex-M0+ MCU, 16kB Flash, 4kB SRAM, USART, I2C, SPI, ACMP, SOIC-20
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K nxp lpc arm microcontroller cortex
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@ -429,561 +429,6 @@ X RTCK 100 -1200 2350 150 R 35 35 1 1 O
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ENDDRAW
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ENDDEF
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#
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# LPC1764FBD100
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#
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DEF LPC1764FBD100 U 0 40 Y Y 1 F N
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F0 "U" -1000 2500 50 H V C CNN
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F1 "LPC1764FBD100" 850 -2600 50 H V C CNN
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F2 "LQFP100" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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S -1050 2450 1050 -2550 0 1 0 f
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X TDO/SWO 1 -1200 2250 150 R 35 35 1 1 O
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X TDI 2 -1200 2150 150 R 35 35 1 1 I
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X TMS/SWDIO 3 -1200 2050 150 R 35 35 1 1 B
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X ~TRST~ 4 -1200 1950 150 R 35 35 1 1 I
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X TCK/SWDCLK 5 -1200 1850 150 R 35 35 1 1 I
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X P0[26]/AD0[3]/RXD3 6 -1200 -1000 150 R 35 35 1 1 B
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X P0[25]/AD0[2]/TXD3 7 -1200 -900 150 R 35 35 1 1 B
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X P0[24]/AD0[1]/CAP3[1] 8 -1200 -800 150 R 35 35 1 1 B
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X P0[23]/AD0[0]/CAP3[0] 9 -1200 -700 150 R 35 35 1 1 B
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X VDDA 10 400 2600 150 D 35 35 1 1 I
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X P1[31]/SCK1/AD0[5] 20 1200 -50 150 L 35 35 1 1 B
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X P0[30]/USB_D- 30 -1200 -1400 150 R 35 35 1 1 B
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X P1[26]/MCOB1/PWM1[6]/CAP0[0] 40 1200 450 150 L 35 35 1 1 B
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X P2[13]/~EINT3~ 50 1200 1750 150 L 35 35 1 1 B
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X P0[18]/DCD1/MOSI0/MOSI 60 -1200 -200 150 R 35 35 1 1 B
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X P2[3]/PWM1[4]/DCD1/TRACEDATA[2] 70 1200 -550 150 L 35 35 1 1 B
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X P0[5]/I2SRX_WS/TD2/CAP2[1] 80 -1200 800 150 R 35 35 1 1 B
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X P1[10]/ENET_RXD1 90 1200 1850 150 L 35 35 1 1 B
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X VSSA 11 400 -2700 150 U 35 35 1 1 W
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X P1[30]/VBUS/AD0[4] 21 1200 50 150 L 35 35 1 1 B
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X VSS 31 -200 -2700 150 U 35 35 1 1 W
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X VSS 41 100 -2700 150 U 35 35 1 1 W
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X P2[12]/~EINT2~ 51 1200 -1450 150 L 35 35 1 1 B
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X P0[17]/CTS1/MISO0/MISO 61 -1200 -100 150 R 35 35 1 1 B
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X VDD(3V3) 71 -200 2600 150 D 35 35 1 1 W
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X P0[4]/I2SRX_CLK/RD2/CAP2[0] 81 -1200 900 150 R 35 35 1 1 B
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X P1[9]/ENET_RXD0 91 1200 1950 150 L 35 35 1 1 B
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X VREFP 12 1200 -2250 150 L 35 35 1 1 W
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X XTAL1 22 -1200 -1600 150 R 35 35 1 1 I
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X P1[18]/USB_UP_LED/PWM1[1]/CAP1[0] 32 1200 1250 150 L 35 35 1 1 B
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X VDD(REG)(3V3) 42 200 2600 150 D 35 35 1 1 W
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X P2[11]/~EINT1~ 52 1200 -1350 150 L 35 35 1 1 B
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X P0[15]/TXD1/SCK0/SCK 62 -1200 100 150 R 35 35 1 1 B
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X VSS 72 0 -2700 150 U 35 35 1 1 W
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X P4[28]/MAT2[0]/TXD3 82 1200 -1950 150 L 35 35 1 1 B
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X P1[8]/ENET_CRS 92 1200 2050 150 L 35 35 1 1 B
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X XTAL2 23 -1200 -1750 150 R 35 35 1 1 I
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X P1[19]/MCOA0/CAP1[1] 33 1200 1150 150 L 35 35 1 1 B
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X P1[27]/CLKOUT/CAP0[1] 43 1200 350 150 L 35 35 1 1 B
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X P2[10]/~EINT0~/NMI 53 1200 -1250 150 L 35 35 1 1 B
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X P0[16]/RXD1/SSEL0/SSEL 63 -1200 0 150 R 35 35 1 1 B
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X P2[2]/PWM1[3]/CTS1/TRACEDATA[3] 73 1200 -450 150 L 35 35 1 1 B
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X VSS 83 -400 -2700 150 U 35 35 1 1 W
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X P1[4]/ENET_TX_EN 93 1200 2150 150 L 35 35 1 1 B
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X ~RSTOUT~ 14 -1200 1500 150 R 35 35 1 1 O
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X P0[28]/SCL0/USB_SCL 24 -1200 -1200 150 R 35 35 1 1 B
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X P1[20]/MCI0/PWM1[2]/SCK0 34 1200 1050 150 L 35 35 1 1 B
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X P1[28]/MCOA2/PCAP1[0]/MAT0[0] 44 1200 250 150 L 35 35 1 1 B
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X VDD(3V3) 54 -300 2600 150 D 35 35 1 1 W
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X P2[9]/USB_CONNECT/RXD2 64 1200 -1150 150 L 35 35 1 1 B
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X P2[1]/PWM1[2]/RXD1 74 1200 -350 150 L 35 35 1 1 B
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X VDD(REG)(3V3) 84 100 2600 150 D 35 35 1 1 W
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X P1[1]/ENET_TDX1 94 1200 2250 150 L 35 35 1 1 B
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X VREFN 15 1200 -2450 150 L 35 35 1 1 W
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X P0[27]/SDA0/USB_SDA 25 -1200 -1100 150 R 35 35 1 1 B
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X P1[21]/~MCABORT~/PWM1[3]/SSEL0 35 1200 950 150 L 35 35 1 1 B
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X P1[29]/MCOB2/PCAP1[1]/MAT0[1] 45 1200 150 150 L 35 35 1 1 B
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X VSS 55 -300 -2700 150 U 35 35 1 1 W
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X P2[8]/TD2/TXD2 65 1200 -1050 150 L 35 35 1 1 B
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X P2[0]/PWM1[1]/TXD1 75 1200 -250 150 L 35 35 1 1 B
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X P4[29]/MAT2[1]/RXD3 85 1200 -2050 150 L 35 35 1 1 B
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X P1[0]/ENET_TXD0 95 1200 2350 150 L 35 35 1 1 B
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X RTCX1 16 -1200 -1950 150 R 35 35 1 1 I
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X P3[26]/STCLK/MAT0[1]/PWM1[3] 26 1200 -1750 150 L 35 35 1 1 B
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X P1[22]/MCOB0/MAT1[0] 36 1200 850 150 L 35 35 1 1 B
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X P0[0]/RD1/TXD3/SDA1 46 -1200 1300 150 R 35 35 1 1 B
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X P0[22]/RTS1/TD1 56 -1200 -600 150 R 35 35 1 1 B
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X P2[7]/RD2/RTS1 66 1200 -950 150 L 35 35 1 1 B
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X P0[9]/MOSI1/MAT2[3] 76 -1200 400 150 R 35 35 1 1 B
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X P1[17]/ENET_MDIO 86 1200 1350 150 L 35 35 1 1 B
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X VDD(3V3) 96 -100 2600 150 D 35 35 1 1 W
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X ~RESET~ 17 -1200 1650 150 R 35 35 1 1 I
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X P3[25]/MAT0[0]/PWM1[2] 27 1200 -1650 150 L 35 35 1 1 B
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X P1[23]/MCI1/PWM1[4]/MISO0 37 1200 750 150 L 35 35 1 1 B
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X P0[1]/TD1/RXD3/SCL1 47 -1200 1200 150 R 35 35 1 1 B
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X P0[21]/RI1/RD1 57 -1200 -500 150 R 35 35 1 1 B
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X P2[6]/PCAP1[0]/RI1/TRACECLK 67 1200 -850 150 L 35 35 1 1 B
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X P0[8]/MISO1/MAT2[2] 77 -1200 500 150 R 35 35 1 1 B
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X P1[16]/ENET_MDC 87 1200 1450 150 L 35 35 1 1 B
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X VSS 97 -100 -2700 150 U 35 35 1 1 W
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X RTCX2 18 -1200 -2100 150 R 35 35 1 1 O
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X VDD(3V3) 28 -400 2600 150 D 35 35 1 1 W
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X P1[24]/MCI2/PWM1[5]/MOSI0 38 1200 650 150 L 35 35 1 1 B
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X P0[10]/TXD2/SDA2/MAT3[0] 48 -1200 300 150 R 35 35 1 1 B
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X P0[20]/DTR1/SCL1 58 -1200 -400 150 R 35 35 1 1 B
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X P2[5]/PWM1[6]/DTR1/TRACEDATA[0] 68 1200 -750 150 L 35 35 1 1 B
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X P0[7]/SCK1/MAT2[1] 78 -1200 600 150 R 35 35 1 1 B
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X P1[15]/ENET_REF_CLK 88 1200 1550 150 L 35 35 1 1 B
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X P0[2]/TXD0/AD0[7] 98 -1200 1100 150 R 35 35 1 1 B
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X VBAT 19 -1200 -2350 150 R 35 35 1 1 I
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X P0[29]/USB_D+ 29 -1200 -1300 150 R 35 35 1 1 B
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X P1[25]/MCOA1/MAT1[1] 39 1200 550 150 L 35 35 1 1 B
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X P0[11]/RXD2/SCL2/MAT3[1] 49 -1200 200 150 R 35 35 1 1 B
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X P0[19]/DSR1/SDA1 59 -1200 -300 150 R 35 35 1 1 B
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X P2[4]/PWM1[5]/DSR1/TRACEDATA[1] 69 1200 -650 150 L 35 35 1 1 B
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X P0[6]/SSEL1/MAT2[0] 79 -1200 700 150 R 35 35 1 1 B
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X P1[14]/ENET_RX_ER 89 1200 1650 150 L 35 35 1 1 B
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X P0[3]/RXD0/AD0[6] 99 -1200 1000 150 R 35 35 1 1 B
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X RTCK 100 -1200 2350 150 R 35 35 1 1 O
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ENDDRAW
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ENDDEF
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#
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# LPC1765FBD100
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#
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DEF LPC1765FBD100 U 0 40 Y Y 1 F N
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F0 "U" -1000 2500 50 H V C CNN
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F1 "LPC1765FBD100" 850 -2600 50 H V C CNN
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F2 "LQFP100" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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S -1050 2450 1050 -2550 0 1 0 f
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X TDO/SWO 1 -1200 2250 150 R 35 35 1 1 O
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X TDI 2 -1200 2150 150 R 35 35 1 1 I
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X TMS/SWDIO 3 -1200 2050 150 R 35 35 1 1 B
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X ~TRST~ 4 -1200 1950 150 R 35 35 1 1 I
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X TCK/SWDCLK 5 -1200 1850 150 R 35 35 1 1 I
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X P0[26]/AD0[3]/AOUT/RXD3 6 -1200 -1000 150 R 35 35 1 1 B
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X P0[25]/AD0[2]/I2SRX_SDA/TXD3 7 -1200 -900 150 R 35 35 1 1 B
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X P0[24]/AD0[1]/I2SRX_WS/CAP3[1] 8 -1200 -800 150 R 35 35 1 1 B
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X P0[23]/AD0[0]/I2SRX_CLK/CAP3[0] 9 -1200 -700 150 R 35 35 1 1 B
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X VDDA 10 400 2600 150 D 35 35 1 1 I
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X P1[31]/SCK1/AD0[5] 20 1200 -50 150 L 35 35 1 1 B
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X P0[30]/USB_D- 30 -1200 -1400 150 R 35 35 1 1 B
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X P1[26]/MCOB1/PWM1[6]/CAP0[0] 40 1200 450 150 L 35 35 1 1 B
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X P2[13]/~EINT3~/I2STX_SDA 50 1200 1750 150 L 35 35 1 1 B
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X P0[18]/DCD1/MOSI0/MOSI 60 -1200 -200 150 R 35 35 1 1 B
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X P2[3]/PWM1[4]/DCD1/TRACEDATA[2] 70 1200 -550 150 L 35 35 1 1 B
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X P0[5]/I2SRX_WS/TD2/CAP2[1] 80 -1200 800 150 R 35 35 1 1 B
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X P1[10] 90 1200 1850 150 L 35 35 1 1 B
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X VSSA 11 400 -2700 150 U 35 35 1 1 W
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X P1[30]/VBUS/AD0[4] 21 1200 50 150 L 35 35 1 1 B
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X VSS 31 -200 -2700 150 U 35 35 1 1 W
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X VSS 41 100 -2700 150 U 35 35 1 1 W
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X P2[12]/~EINT2~/I2STX_WS 51 1200 -1450 150 L 35 35 1 1 B
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X P0[17]/CTS1/MISO0/MISO 61 -1200 -100 150 R 35 35 1 1 B
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X VDD(3V3) 71 -200 2600 150 D 35 35 1 1 W
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X P0[4]/I2SRX_CLK/RD2/CAP2[0] 81 -1200 900 150 R 35 35 1 1 B
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X P1[9] 91 1200 1950 150 L 35 35 1 1 B
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X VREFP 12 1200 -2250 150 L 35 35 1 1 W
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X XTAL1 22 -1200 -1600 150 R 35 35 1 1 I
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X P1[18]/USB_UP_LED/PWM1[1]/CAP1[0] 32 1200 1250 150 L 35 35 1 1 B
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X VDD(REG)(3V3) 42 200 2600 150 D 35 35 1 1 W
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X P2[11]/~EINT1~/I2STX_CLK 52 1200 -1350 150 L 35 35 1 1 B
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X P0[15]/TXD1/SCK0/SCK 62 -1200 100 150 R 35 35 1 1 B
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X VSS 72 0 -2700 150 U 35 35 1 1 W
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X P4[28]/RX_MCLK/MAT2[0]/TXD3 82 1200 -1950 150 L 35 35 1 1 B
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X P1[8] 92 1200 2050 150 L 35 35 1 1 B
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X XTAL2 23 -1200 -1750 150 R 35 35 1 1 I
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X P1[19]/MCOA0/~USB_PPWR~/CAP1[1] 33 1200 1150 150 L 35 35 1 1 B
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X P1[27]/CLKOUT/~USB_OVRCR~/CAP0[1] 43 1200 350 150 L 35 35 1 1 B
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X P2[10]/~EINT0~/NMI 53 1200 -1250 150 L 35 35 1 1 B
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X P0[16]/RXD1/SSEL0/SSEL 63 -1200 0 150 R 35 35 1 1 B
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X P2[2]/PWM1[3]/CTS1/TRACEDATA[3] 73 1200 -450 150 L 35 35 1 1 B
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X VSS 83 -400 -2700 150 U 35 35 1 1 W
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X P1[4] 93 1200 2150 150 L 35 35 1 1 B
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X ~RSTOUT~ 14 -1200 1500 150 R 35 35 1 1 O
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X P0[28]/SCL0/USB_SCL 24 -1200 -1200 150 R 35 35 1 1 B
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X P1[20]/MCI0/PWM1[2]/SCK0 34 1200 1050 150 L 35 35 1 1 B
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X P1[28]/MCOA2/PCAP1[0]/MAT0[0] 44 1200 250 150 L 35 35 1 1 B
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X VDD(3V3) 54 -300 2600 150 D 35 35 1 1 W
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X P2[9]/USB_CONNECT/RXD2 64 1200 -1150 150 L 35 35 1 1 B
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X P2[1]/PWM1[2]/RXD1 74 1200 -350 150 L 35 35 1 1 B
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X VDD(REG)(3V3) 84 100 2600 150 D 35 35 1 1 W
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X P1[1] 94 1200 2250 150 L 35 35 1 1 B
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X VREFN 15 1200 -2450 150 L 35 35 1 1 W
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X P0[27]/SDA0/USB_SDA 25 -1200 -1100 150 R 35 35 1 1 B
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X P1[21]/~MCABORT~/PWM1[3]/SSEL0 35 1200 950 150 L 35 35 1 1 B
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X P1[29]/MCOB2/PCAP1[1]/MAT0[1] 45 1200 150 150 L 35 35 1 1 B
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X VSS 55 -300 -2700 150 U 35 35 1 1 W
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X P2[8]/TD2/TXD2 65 1200 -1050 150 L 35 35 1 1 B
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X P2[0]/PWM1[1]/TXD1 75 1200 -250 150 L 35 35 1 1 B
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X P4[29]/TX_MCLK/MAT2[1]/RXD3 85 1200 -2050 150 L 35 35 1 1 B
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X P1[0] 95 1200 2350 150 L 35 35 1 1 B
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X RTCX1 16 -1200 -1950 150 R 35 35 1 1 I
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X P3[26]/STCLK/MAT0[1]/PWM1[3] 26 1200 -1750 150 L 35 35 1 1 B
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X P1[22]/MCOB0/USB_PWRD/MAT1[0] 36 1200 850 150 L 35 35 1 1 B
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X P0[0]/RD1/TXD3/SDA1 46 -1200 1300 150 R 35 35 1 1 B
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X P0[22]/RTS1/TD1 56 -1200 -600 150 R 35 35 1 1 B
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X P2[7]/RD2/RTS1 66 1200 -950 150 L 35 35 1 1 B
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X P0[9]/I2STX_SDA/MOSI1/MAT2[3] 76 -1200 400 150 R 35 35 1 1 B
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X P1[17] 86 1200 1350 150 L 35 35 1 1 B
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X VDD(3V3) 96 -100 2600 150 D 35 35 1 1 W
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X ~RESET~ 17 -1200 1650 150 R 35 35 1 1 I
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X P3[25]/MAT0[0]/PWM1[2] 27 1200 -1650 150 L 35 35 1 1 B
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X P1[23]/MCI1/PWM1[4]/MISO0 37 1200 750 150 L 35 35 1 1 B
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X P0[1]/TD1/RXD3/SCL1 47 -1200 1200 150 R 35 35 1 1 B
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X P0[21]/RI1/RD1 57 -1200 -500 150 R 35 35 1 1 B
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X P2[6]/PCAP1[0]/RI1/TRACECLK 67 1200 -850 150 L 35 35 1 1 B
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X P0[8]/I2STX_WS/MISO1/MAT2[2] 77 -1200 500 150 R 35 35 1 1 B
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X P1[16] 87 1200 1450 150 L 35 35 1 1 B
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X VSS 97 -100 -2700 150 U 35 35 1 1 W
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X RTCX2 18 -1200 -2100 150 R 35 35 1 1 O
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X VDD(3V3) 28 -400 2600 150 D 35 35 1 1 W
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X P1[24]/MCI2/PWM1[5]/MOSI0 38 1200 650 150 L 35 35 1 1 B
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X P0[10]/TXD2/SDA2/MAT3[0] 48 -1200 300 150 R 35 35 1 1 B
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X P0[20]/DTR1/SCL1 58 -1200 -400 150 R 35 35 1 1 B
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X P2[5]/PWM1[6]/DTR1/TRACEDATA[0] 68 1200 -750 150 L 35 35 1 1 B
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X P0[7]/I2STX_CLK/SCK1/MAT2[1] 78 -1200 600 150 R 35 35 1 1 B
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X P1[15] 88 1200 1550 150 L 35 35 1 1 B
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X P0[2]/TXD0/AD0[7] 98 -1200 1100 150 R 35 35 1 1 B
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X VBAT 19 -1200 -2350 150 R 35 35 1 1 I
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X P0[29]/USB_D+ 29 -1200 -1300 150 R 35 35 1 1 B
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X P1[25]/MCOA1/MAT1[1] 39 1200 550 150 L 35 35 1 1 B
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X P0[11]/RXD2/SCL2/MAT3[1] 49 -1200 200 150 R 35 35 1 1 B
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X P0[19]/DSR1/SDA1 59 -1200 -300 150 R 35 35 1 1 B
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X P2[4]/PWM1[5]/DSR1/TRACEDATA[1] 69 1200 -650 150 L 35 35 1 1 B
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X P0[6]/I2SRX_SDA/SSEL1/MAT2[0] 79 -1200 700 150 R 35 35 1 1 B
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X P1[14] 89 1200 1650 150 L 35 35 1 1 B
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X P0[3]/RXD0/AD0[6] 99 -1200 1000 150 R 35 35 1 1 B
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X RTCK 100 -1200 2350 150 R 35 35 1 1 O
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ENDDRAW
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ENDDEF
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#
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# LPC1766FBD100
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#
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||||
DEF LPC1766FBD100 U 0 40 Y Y 1 F N
|
||||
F0 "U" -1000 2500 50 H V C CNN
|
||||
F1 "LPC1766FBD100" 850 -2600 50 H V C CNN
|
||||
F2 "LQFP100" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
S -1050 2450 1050 -2550 0 1 0 f
|
||||
X TDO/SWO 1 -1200 2250 150 R 35 35 1 1 O
|
||||
X TDI 2 -1200 2150 150 R 35 35 1 1 I
|
||||
X TMS/SWDIO 3 -1200 2050 150 R 35 35 1 1 B
|
||||
X ~TRST~ 4 -1200 1950 150 R 35 35 1 1 I
|
||||
X TCK/SWDCLK 5 -1200 1850 150 R 35 35 1 1 I
|
||||
X P0[26]/AD0[3]/AOUT/RXD3 6 -1200 -1000 150 R 35 35 1 1 B
|
||||
X P0[25]/AD0[2]/I2SRX_SDA/TXD3 7 -1200 -900 150 R 35 35 1 1 B
|
||||
X P0[24]/AD0[1]/I2SRX_WS/CAP3[1] 8 -1200 -800 150 R 35 35 1 1 B
|
||||
X P0[23]/AD0[0]/I2SRX_CLK/CAP3[0] 9 -1200 -700 150 R 35 35 1 1 B
|
||||
X VDDA 10 400 2600 150 D 35 35 1 1 I
|
||||
X P1[31]/SCK1/AD0[5] 20 1200 -50 150 L 35 35 1 1 B
|
||||
X P0[30]/USB_D- 30 -1200 -1400 150 R 35 35 1 1 B
|
||||
X P1[26]/MCOB1/PWM1[6]/CAP0[0] 40 1200 450 150 L 35 35 1 1 B
|
||||
X P2[13]/~EINT3~/I2STX_SDA 50 1200 1750 150 L 35 35 1 1 B
|
||||
X P0[18]/DCD1/MOSI0/MOSI 60 -1200 -200 150 R 35 35 1 1 B
|
||||
X P2[3]/PWM1[4]/DCD1/TRACEDATA[2] 70 1200 -550 150 L 35 35 1 1 B
|
||||
X P0[5]/I2SRX_WS/TD2/CAP2[1] 80 -1200 800 150 R 35 35 1 1 B
|
||||
X P1[10]/ENET_RXD1 90 1200 1850 150 L 35 35 1 1 B
|
||||
X VSSA 11 400 -2700 150 U 35 35 1 1 W
|
||||
X P1[30]/VBUS/AD0[4] 21 1200 50 150 L 35 35 1 1 B
|
||||
X VSS 31 -200 -2700 150 U 35 35 1 1 W
|
||||
X VSS 41 100 -2700 150 U 35 35 1 1 W
|
||||
X P2[12]/~EINT2~/I2STX_WS 51 1200 -1450 150 L 35 35 1 1 B
|
||||
X P0[17]/CTS1/MISO0/MISO 61 -1200 -100 150 R 35 35 1 1 B
|
||||
X VDD(3V3) 71 -200 2600 150 D 35 35 1 1 W
|
||||
X P0[4]/I2SRX_CLK/RD2/CAP2[0] 81 -1200 900 150 R 35 35 1 1 B
|
||||
X P1[9]/ENET_RXD0 91 1200 1950 150 L 35 35 1 1 B
|
||||
X VREFP 12 1200 -2250 150 L 35 35 1 1 W
|
||||
X XTAL1 22 -1200 -1600 150 R 35 35 1 1 I
|
||||
X P1[18]/USB_UP_LED/PWM1[1]/CAP1[0] 32 1200 1250 150 L 35 35 1 1 B
|
||||
X VDD(REG)(3V3) 42 200 2600 150 D 35 35 1 1 W
|
||||
X P2[11]/~EINT1~/I2STX_CLK 52 1200 -1350 150 L 35 35 1 1 B
|
||||
X P0[15]/TXD1/SCK0/SCK 62 -1200 100 150 R 35 35 1 1 B
|
||||
X VSS 72 0 -2700 150 U 35 35 1 1 W
|
||||
X P4[28]/RX_MCLK/MAT2[0]/TXD3 82 1200 -1950 150 L 35 35 1 1 B
|
||||
X P1[8]/ENET_CRS 92 1200 2050 150 L 35 35 1 1 B
|
||||
X XTAL2 23 -1200 -1750 150 R 35 35 1 1 I
|
||||
X P1[19]/MCOA0/~USB_PPWR~/CAP1[1] 33 1200 1150 150 L 35 35 1 1 B
|
||||
X P1[27]/CLKOUT/~USB_OVRCR~/CAP0[1] 43 1200 350 150 L 35 35 1 1 B
|
||||
X P2[10]/~EINT0~/NMI 53 1200 -1250 150 L 35 35 1 1 B
|
||||
X P0[16]/RXD1/SSEL0/SSEL 63 -1200 0 150 R 35 35 1 1 B
|
||||
X P2[2]/PWM1[3]/CTS1/TRACEDATA[3] 73 1200 -450 150 L 35 35 1 1 B
|
||||
X VSS 83 -400 -2700 150 U 35 35 1 1 W
|
||||
X P1[4]/ENET_TX_EN 93 1200 2150 150 L 35 35 1 1 B
|
||||
X ~RSTOUT~ 14 -1200 1500 150 R 35 35 1 1 O
|
||||
X P0[28]/SCL0/USB_SCL 24 -1200 -1200 150 R 35 35 1 1 B
|
||||
X P1[20]/MCI0/PWM1[2]/SCK0 34 1200 1050 150 L 35 35 1 1 B
|
||||
X P1[28]/MCOA2/PCAP1[0]/MAT0[0] 44 1200 250 150 L 35 35 1 1 B
|
||||
X VDD(3V3) 54 -300 2600 150 D 35 35 1 1 W
|
||||
X P2[9]/USB_CONNECT/RXD2 64 1200 -1150 150 L 35 35 1 1 B
|
||||
X P2[1]/PWM1[2]/RXD1 74 1200 -350 150 L 35 35 1 1 B
|
||||
X VDD(REG)(3V3) 84 100 2600 150 D 35 35 1 1 W
|
||||
X P1[1]/ENET_TDX1 94 1200 2250 150 L 35 35 1 1 B
|
||||
X VREFN 15 1200 -2450 150 L 35 35 1 1 W
|
||||
X P0[27]/SDA0/USB_SDA 25 -1200 -1100 150 R 35 35 1 1 B
|
||||
X P1[21]/~MCABORT~/PWM1[3]/SSEL0 35 1200 950 150 L 35 35 1 1 B
|
||||
X P1[29]/MCOB2/PCAP1[1]/MAT0[1] 45 1200 150 150 L 35 35 1 1 B
|
||||
X VSS 55 -300 -2700 150 U 35 35 1 1 W
|
||||
X P2[8]/TD2/TXD2 65 1200 -1050 150 L 35 35 1 1 B
|
||||
X P2[0]/PWM1[1]/TXD1 75 1200 -250 150 L 35 35 1 1 B
|
||||
X P4[29]/TX_MCLK/MAT2[1]/RXD3 85 1200 -2050 150 L 35 35 1 1 B
|
||||
X P1[0]/ENET_TXD0 95 1200 2350 150 L 35 35 1 1 B
|
||||
X RTCX1 16 -1200 -1950 150 R 35 35 1 1 I
|
||||
X P3[26]/STCLK/MAT0[1]/PWM1[3] 26 1200 -1750 150 L 35 35 1 1 B
|
||||
X P1[22]/MCOB0/USB_PWRD/MAT1[0] 36 1200 850 150 L 35 35 1 1 B
|
||||
X P0[0]/RD1/TXD3/SDA1 46 -1200 1300 150 R 35 35 1 1 B
|
||||
X P0[22]/RTS1/TD1 56 -1200 -600 150 R 35 35 1 1 B
|
||||
X P2[7]/RD2/RTS1 66 1200 -950 150 L 35 35 1 1 B
|
||||
X P0[9]/I2STX_SDA/MOSI1/MAT2[3] 76 -1200 400 150 R 35 35 1 1 B
|
||||
X P1[17]/ENET_MDIO 86 1200 1350 150 L 35 35 1 1 B
|
||||
X VDD(3V3) 96 -100 2600 150 D 35 35 1 1 W
|
||||
X ~RESET~ 17 -1200 1650 150 R 35 35 1 1 I
|
||||
X P3[25]/MAT0[0]/PWM1[2] 27 1200 -1650 150 L 35 35 1 1 B
|
||||
X P1[23]/MCI1/PWM1[4]/MISO0 37 1200 750 150 L 35 35 1 1 B
|
||||
X P0[1]/TD1/RXD3/SCL1 47 -1200 1200 150 R 35 35 1 1 B
|
||||
X P0[21]/RI1/RD1 57 -1200 -500 150 R 35 35 1 1 B
|
||||
X P2[6]/PCAP1[0]/RI1/TRACECLK 67 1200 -850 150 L 35 35 1 1 B
|
||||
X P0[8]/I2STX_WS/MISO1/MAT2[2] 77 -1200 500 150 R 35 35 1 1 B
|
||||
X P1[16]/ENET_MDC 87 1200 1450 150 L 35 35 1 1 B
|
||||
X VSS 97 -100 -2700 150 U 35 35 1 1 W
|
||||
X RTCX2 18 -1200 -2100 150 R 35 35 1 1 O
|
||||
X VDD(3V3) 28 -400 2600 150 D 35 35 1 1 W
|
||||
X P1[24]/MCI2/PWM1[5]/MOSI0 38 1200 650 150 L 35 35 1 1 B
|
||||
X P0[10]/TXD2/SDA2/MAT3[0] 48 -1200 300 150 R 35 35 1 1 B
|
||||
X P0[20]/DTR1/SCL1 58 -1200 -400 150 R 35 35 1 1 B
|
||||
X P2[5]/PWM1[6]/DTR1/TRACEDATA[0] 68 1200 -750 150 L 35 35 1 1 B
|
||||
X P0[7]/I2STX_CLK/SCK1/MAT2[1] 78 -1200 600 150 R 35 35 1 1 B
|
||||
X P1[15]/ENET_REF_CLK 88 1200 1550 150 L 35 35 1 1 B
|
||||
X P0[2]/TXD0/AD0[7] 98 -1200 1100 150 R 35 35 1 1 B
|
||||
X VBAT 19 -1200 -2350 150 R 35 35 1 1 I
|
||||
X P0[29]/USB_D+ 29 -1200 -1300 150 R 35 35 1 1 B
|
||||
X P1[25]/MCOA1/MAT1[1] 39 1200 550 150 L 35 35 1 1 B
|
||||
X P0[11]/RXD2/SCL2/MAT3[1] 49 -1200 200 150 R 35 35 1 1 B
|
||||
X P0[19]/DSR1/SDA1 59 -1200 -300 150 R 35 35 1 1 B
|
||||
X P2[4]/PWM1[5]/DSR1/TRACEDATA[1] 69 1200 -650 150 L 35 35 1 1 B
|
||||
X P0[6]/I2SRX_SDA/SSEL1/MAT2[0] 79 -1200 700 150 R 35 35 1 1 B
|
||||
X P1[14]/ENET_RX_ER 89 1200 1650 150 L 35 35 1 1 B
|
||||
X P0[3]/RXD0/AD0[6] 99 -1200 1000 150 R 35 35 1 1 B
|
||||
X RTCK 100 -1200 2350 150 R 35 35 1 1 O
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# LPC1767FBD100
|
||||
#
|
||||
DEF LPC1767FBD100 U 0 40 Y Y 1 F N
|
||||
F0 "U" -1000 2500 50 H V C CNN
|
||||
F1 "LPC1767FBD100" 850 -2600 50 H V C CNN
|
||||
F2 "LQFP100" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
S -1050 2450 1050 -2550 0 1 0 f
|
||||
X TDO/SWO 1 -1200 2250 150 R 35 35 1 1 O
|
||||
X TDI 2 -1200 2150 150 R 35 35 1 1 I
|
||||
X TMS/SWDIO 3 -1200 2050 150 R 35 35 1 1 B
|
||||
X ~TRST~ 4 -1200 1950 150 R 35 35 1 1 I
|
||||
X TCK/SWDCLK 5 -1200 1850 150 R 35 35 1 1 I
|
||||
X P0[26]/AD0[3]/AOUT/RXD3 6 -1200 -1000 150 R 35 35 1 1 B
|
||||
X P0[25]/AD0[2]/I2SRX_SDA/TXD3 7 -1200 -900 150 R 35 35 1 1 B
|
||||
X P0[24]/AD0[1]/I2SRX_WS/CAP3[1] 8 -1200 -800 150 R 35 35 1 1 B
|
||||
X P0[23]/AD0[0]/I2SRX_CLK/CAP3[0] 9 -1200 -700 150 R 35 35 1 1 B
|
||||
X VDDA 10 400 2600 150 D 35 35 1 1 I
|
||||
X P1[31]/SCK1/AD0[5] 20 1200 -50 150 L 35 35 1 1 B
|
||||
X P0[30] 30 -1200 -1400 150 R 35 35 1 1 B
|
||||
X P1[26]/MCOB1/PWM1[6]/CAP0[0] 40 1200 450 150 L 35 35 1 1 B
|
||||
X P2[13]/~EINT3~/I2STX_SDA 50 1200 1750 150 L 35 35 1 1 B
|
||||
X P0[18]/DCD1/MOSI0/MOSI 60 -1200 -200 150 R 35 35 1 1 B
|
||||
X P2[3]/PWM1[4]/DCD1/TRACEDATA[2] 70 1200 -550 150 L 35 35 1 1 B
|
||||
X P0[5]/I2SRX_WS/CAP2[1] 80 -1200 800 150 R 35 35 1 1 B
|
||||
X P1[10]/ENET_RXD1 90 1200 1850 150 L 35 35 1 1 B
|
||||
X VSSA 11 400 -2700 150 U 35 35 1 1 W
|
||||
X P1[30]/AD0[4] 21 1200 50 150 L 35 35 1 1 B
|
||||
X VSS 31 -200 -2700 150 U 35 35 1 1 W
|
||||
X VSS 41 100 -2700 150 U 35 35 1 1 W
|
||||
X P2[12]/~EINT2~/I2STX_WS 51 1200 -1450 150 L 35 35 1 1 B
|
||||
X P0[17]/CTS1/MISO0/MISO 61 -1200 -100 150 R 35 35 1 1 B
|
||||
X VDD(3V3) 71 -200 2600 150 D 35 35 1 1 W
|
||||
X P0[4]/I2SRX_CLK/CAP2[0] 81 -1200 900 150 R 35 35 1 1 B
|
||||
X P1[9]/ENET_RXD0 91 1200 1950 150 L 35 35 1 1 B
|
||||
X VREFP 12 1200 -2250 150 L 35 35 1 1 W
|
||||
X XTAL1 22 -1200 -1600 150 R 35 35 1 1 I
|
||||
X P1[18]/PWM1[1]/CAP1[0] 32 1200 1250 150 L 35 35 1 1 B
|
||||
X VDD(REG)(3V3) 42 200 2600 150 D 35 35 1 1 W
|
||||
X P2[11]/~EINT1~/I2STX_CLK 52 1200 -1350 150 L 35 35 1 1 B
|
||||
X P0[15]/TXD1/SCK0/SCK 62 -1200 100 150 R 35 35 1 1 B
|
||||
X VSS 72 0 -2700 150 U 35 35 1 1 W
|
||||
X P4[28]/RX_MCLK/MAT2[0]/TXD3 82 1200 -1950 150 L 35 35 1 1 B
|
||||
X P1[8]/ENET_CRS 92 1200 2050 150 L 35 35 1 1 B
|
||||
X XTAL2 23 -1200 -1750 150 R 35 35 1 1 I
|
||||
X P1[19]/MCOA0/CAP1[1] 33 1200 1150 150 L 35 35 1 1 B
|
||||
X P1[27]/CLKOUT/CAP0[1] 43 1200 350 150 L 35 35 1 1 B
|
||||
X P2[10]/~EINT0~/NMI 53 1200 -1250 150 L 35 35 1 1 B
|
||||
X P0[16]/RXD1/SSEL0/SSEL 63 -1200 0 150 R 35 35 1 1 B
|
||||
X P2[2]/PWM1[3]/CTS1/TRACEDATA[3] 73 1200 -450 150 L 35 35 1 1 B
|
||||
X VSS 83 -400 -2700 150 U 35 35 1 1 W
|
||||
X P1[4]/ENET_TX_EN 93 1200 2150 150 L 35 35 1 1 B
|
||||
X ~RSTOUT~ 14 -1200 1500 150 R 35 35 1 1 O
|
||||
X P0[28]/SCL0 24 -1200 -1200 150 R 35 35 1 1 B
|
||||
X P1[20]/MCI0/PWM1[2]/SCK0 34 1200 1050 150 L 35 35 1 1 B
|
||||
X P1[28]/MCOA2/PCAP1[0]/MAT0[0] 44 1200 250 150 L 35 35 1 1 B
|
||||
X VDD(3V3) 54 -300 2600 150 D 35 35 1 1 W
|
||||
X P2[9]/USB_CONNECT/RXD2 64 1200 -1150 150 L 35 35 1 1 B
|
||||
X P2[1]/PWM1[2]/RXD1 74 1200 -350 150 L 35 35 1 1 B
|
||||
X VDD(REG)(3V3) 84 100 2600 150 D 35 35 1 1 W
|
||||
X P1[1]/ENET_TDX1 94 1200 2250 150 L 35 35 1 1 B
|
||||
X VREFN 15 1200 -2450 150 L 35 35 1 1 W
|
||||
X P0[27]/SDA0 25 -1200 -1100 150 R 35 35 1 1 B
|
||||
X P1[21]/~MCABORT~/PWM1[3]/SSEL0 35 1200 950 150 L 35 35 1 1 B
|
||||
X P1[29]/MCOB2/PCAP1[1]/MAT0[1] 45 1200 150 150 L 35 35 1 1 B
|
||||
X VSS 55 -300 -2700 150 U 35 35 1 1 W
|
||||
X P2[8]/TXD2 65 1200 -1050 150 L 35 35 1 1 B
|
||||
X P2[0]/PWM1[1]/TXD1 75 1200 -250 150 L 35 35 1 1 B
|
||||
X P4[29]/TX_MCLK/MAT2[1]/RXD3 85 1200 -2050 150 L 35 35 1 1 B
|
||||
X P1[0]/ENET_TXD0 95 1200 2350 150 L 35 35 1 1 B
|
||||
X RTCX1 16 -1200 -1950 150 R 35 35 1 1 I
|
||||
X P3[26]/STCLK/MAT0[1]/PWM1[3] 26 1200 -1750 150 L 35 35 1 1 B
|
||||
X P1[22]/MCOB0/MAT1[0] 36 1200 850 150 L 35 35 1 1 B
|
||||
X P0[0]/TXD3/SDA1 46 -1200 1300 150 R 35 35 1 1 B
|
||||
X P0[22]/RTS1 56 -1200 -600 150 R 35 35 1 1 B
|
||||
X P2[7]/RTS1 66 1200 -950 150 L 35 35 1 1 B
|
||||
X P0[9]/I2STX_SDA/MOSI1/MAT2[3] 76 -1200 400 150 R 35 35 1 1 B
|
||||
X P1[17]/ENET_MDIO 86 1200 1350 150 L 35 35 1 1 B
|
||||
X VDD(3V3) 96 -100 2600 150 D 35 35 1 1 W
|
||||
X ~RESET~ 17 -1200 1650 150 R 35 35 1 1 I
|
||||
X P3[25]/MAT0[0]/PWM1[2] 27 1200 -1650 150 L 35 35 1 1 B
|
||||
X P1[23]/MCI1/PWM1[4]/MISO0 37 1200 750 150 L 35 35 1 1 B
|
||||
X P0[1]/RXD3/SCL1 47 -1200 1200 150 R 35 35 1 1 B
|
||||
X P0[21]/RI1 57 -1200 -500 150 R 35 35 1 1 B
|
||||
X P2[6]/PCAP1[0]/RI1/TRACECLK 67 1200 -850 150 L 35 35 1 1 B
|
||||
X P0[8]/I2STX_WS/MISO1/MAT2[2] 77 -1200 500 150 R 35 35 1 1 B
|
||||
X P1[16]/ENET_MDC 87 1200 1450 150 L 35 35 1 1 B
|
||||
X VSS 97 -100 -2700 150 U 35 35 1 1 W
|
||||
X RTCX2 18 -1200 -2100 150 R 35 35 1 1 O
|
||||
X VDD(3V3) 28 -400 2600 150 D 35 35 1 1 W
|
||||
X P1[24]/MCI2/PWM1[5]/MOSI0 38 1200 650 150 L 35 35 1 1 B
|
||||
X P0[10]/TXD2/SDA2/MAT3[0] 48 -1200 300 150 R 35 35 1 1 B
|
||||
X P0[20]/DTR1/SCL1 58 -1200 -400 150 R 35 35 1 1 B
|
||||
X P2[5]/PWM1[6]/DTR1/TRACEDATA[0] 68 1200 -750 150 L 35 35 1 1 B
|
||||
X P0[7]/I2STX_CLK/SCK1/MAT2[1] 78 -1200 600 150 R 35 35 1 1 B
|
||||
X P1[15]/ENET_REF_CLK 88 1200 1550 150 L 35 35 1 1 B
|
||||
X P0[2]/TXD0/AD0[7] 98 -1200 1100 150 R 35 35 1 1 B
|
||||
X VBAT 19 -1200 -2350 150 R 35 35 1 1 I
|
||||
X P0[29] 29 -1200 -1300 150 R 35 35 1 1 B
|
||||
X P1[25]/MCOA1/MAT1[1] 39 1200 550 150 L 35 35 1 1 B
|
||||
X P0[11]/RXD2/SCL2/MAT3[1] 49 -1200 200 150 R 35 35 1 1 B
|
||||
X P0[19]/DSR1/SDA1 59 -1200 -300 150 R 35 35 1 1 B
|
||||
X P2[4]/PWM1[5]/DSR1/TRACEDATA[1] 69 1200 -650 150 L 35 35 1 1 B
|
||||
X P0[6]/I2SRX_SDA/SSEL1/MAT2[0] 79 -1200 700 150 R 35 35 1 1 B
|
||||
X P1[14]/ENET_RX_ER 89 1200 1650 150 L 35 35 1 1 B
|
||||
X P0[3]/RXD0/AD0[6] 99 -1200 1000 150 R 35 35 1 1 B
|
||||
X RTCK 100 -1200 2350 150 R 35 35 1 1 O
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# LPC1769FBD100
|
||||
#
|
||||
DEF LPC1769FBD100 U 0 40 Y Y 1 F N
|
||||
F0 "U" -1000 2500 50 H V C CNN
|
||||
F1 "LPC1769FBD100" 850 -2600 50 H V C CNN
|
||||
F2 "LQFP100" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
S -1050 2450 1050 -2550 0 1 0 f
|
||||
X TDO/SWO 1 -1200 2250 150 R 35 35 1 1 O
|
||||
X TDI 2 -1200 2150 150 R 35 35 1 1 I
|
||||
X TMS/SWDIO 3 -1200 2050 150 R 35 35 1 1 B
|
||||
X ~TRST~ 4 -1200 1950 150 R 35 35 1 1 I
|
||||
X TCK/SWDCLK 5 -1200 1850 150 R 35 35 1 1 I
|
||||
X P0[26]/AD0[3]/AOUT/RXD3 6 -1200 -1000 150 R 35 35 1 1 B
|
||||
X P0[25]/AD0[2]/I2SRX_SDA/TXD3 7 -1200 -900 150 R 35 35 1 1 B
|
||||
X P0[24]/AD0[1]/I2SRX_WS/CAP3[1] 8 -1200 -800 150 R 35 35 1 1 B
|
||||
X P0[23]/AD0[0]/I2SRX_CLK/CAP3[0] 9 -1200 -700 150 R 35 35 1 1 B
|
||||
X VDDA 10 400 2600 150 D 35 35 1 1 I
|
||||
X P1[31]/SCK1/AD0[5] 20 1200 -50 150 L 35 35 1 1 B
|
||||
X P0[30]/USB_D- 30 -1200 -1400 150 R 35 35 1 1 B
|
||||
X P1[26]/MCOB1/PWM1[6]/CAP0[0] 40 1200 450 150 L 35 35 1 1 B
|
||||
X P2[13]/~EINT3~/I2STX_SDA 50 1200 1750 150 L 35 35 1 1 B
|
||||
X P0[18]/DCD1/MOSI0/MOSI 60 -1200 -200 150 R 35 35 1 1 B
|
||||
X P2[3]/PWM1[4]/DCD1/TRACEDATA[2] 70 1200 -550 150 L 35 35 1 1 B
|
||||
X P0[5]/I2SRX_WS/TD2/CAP2[1] 80 -1200 800 150 R 35 35 1 1 B
|
||||
X P1[10]/ENET_RXD1 90 1200 1850 150 L 35 35 1 1 B
|
||||
X VSSA 11 400 -2700 150 U 35 35 1 1 W
|
||||
X P1[30]/VBUS/AD0[4] 21 1200 50 150 L 35 35 1 1 B
|
||||
X VSS 31 -200 -2700 150 U 35 35 1 1 W
|
||||
X VSS 41 100 -2700 150 U 35 35 1 1 W
|
||||
X P2[12]/~EINT2~/I2STX_WS 51 1200 -1450 150 L 35 35 1 1 B
|
||||
X P0[17]/CTS1/MISO0/MISO 61 -1200 -100 150 R 35 35 1 1 B
|
||||
X VDD(3V3) 71 -200 2600 150 D 35 35 1 1 W
|
||||
X P0[4]/I2SRX_CLK/RD2/CAP2[0] 81 -1200 900 150 R 35 35 1 1 B
|
||||
X P1[9]/ENET_RXD0 91 1200 1950 150 L 35 35 1 1 B
|
||||
X VREFP 12 1200 -2250 150 L 35 35 1 1 W
|
||||
X XTAL1 22 -1200 -1600 150 R 35 35 1 1 I
|
||||
X P1[18]/USB_UP_LED/PWM1[1]/CAP1[0] 32 1200 1250 150 L 35 35 1 1 B
|
||||
X VDD(REG)(3V3) 42 200 2600 150 D 35 35 1 1 W
|
||||
X P2[11]/~EINT1~/I2STX_CLK 52 1200 -1350 150 L 35 35 1 1 B
|
||||
X P0[15]/TXD1/SCK0/SCK 62 -1200 100 150 R 35 35 1 1 B
|
||||
X VSS 72 0 -2700 150 U 35 35 1 1 W
|
||||
X P4[28]/RX_MCLK/MAT2[0]/TXD3 82 1200 -1950 150 L 35 35 1 1 B
|
||||
X P1[8]/ENET_CRS 92 1200 2050 150 L 35 35 1 1 B
|
||||
X XTAL2 23 -1200 -1750 150 R 35 35 1 1 I
|
||||
X P1[19]/MCOA0/~USB_PPWR~/CAP1[1] 33 1200 1150 150 L 35 35 1 1 B
|
||||
X P1[27]/CLKOUT/~USB_OVRCR~/CAP0[1] 43 1200 350 150 L 35 35 1 1 B
|
||||
X P2[10]/~EINT0~/NMI 53 1200 -1250 150 L 35 35 1 1 B
|
||||
X P0[16]/RXD1/SSEL0/SSEL 63 -1200 0 150 R 35 35 1 1 B
|
||||
X P2[2]/PWM1[3]/CTS1/TRACEDATA[3] 73 1200 -450 150 L 35 35 1 1 B
|
||||
X VSS 83 -400 -2700 150 U 35 35 1 1 W
|
||||
X P1[4]/ENET_TX_EN 93 1200 2150 150 L 35 35 1 1 B
|
||||
X ~RSTOUT~ 14 -1200 1500 150 R 35 35 1 1 O
|
||||
X P0[28]/SCL0/USB_SCL 24 -1200 -1200 150 R 35 35 1 1 B
|
||||
X P1[20]/MCI0/PWM1[2]/SCK0 34 1200 1050 150 L 35 35 1 1 B
|
||||
X P1[28]/MCOA2/PCAP1[0]/MAT0[0] 44 1200 250 150 L 35 35 1 1 B
|
||||
X VDD(3V3) 54 -300 2600 150 D 35 35 1 1 W
|
||||
X P2[9]/USB_CONNECT/RXD2 64 1200 -1150 150 L 35 35 1 1 B
|
||||
X P2[1]/PWM1[2]/RXD1 74 1200 -350 150 L 35 35 1 1 B
|
||||
X VDD(REG)(3V3) 84 100 2600 150 D 35 35 1 1 W
|
||||
X P1[1]/ENET_TDX1 94 1200 2250 150 L 35 35 1 1 B
|
||||
X VREFN 15 1200 -2450 150 L 35 35 1 1 W
|
||||
X P0[27]/SDA0/USB_SDA 25 -1200 -1100 150 R 35 35 1 1 B
|
||||
X P1[21]/~MCABORT~/PWM1[3]/SSEL0 35 1200 950 150 L 35 35 1 1 B
|
||||
X P1[29]/MCOB2/PCAP1[1]/MAT0[1] 45 1200 150 150 L 35 35 1 1 B
|
||||
X VSS 55 -300 -2700 150 U 35 35 1 1 W
|
||||
X P2[8]/TD2/TXD2 65 1200 -1050 150 L 35 35 1 1 B
|
||||
X P2[0]/PWM1[1]/TXD1 75 1200 -250 150 L 35 35 1 1 B
|
||||
X P4[29]/TX_MCLK/MAT2[1]/RXD3 85 1200 -2050 150 L 35 35 1 1 B
|
||||
X P1[0]/ENET_TXD0 95 1200 2350 150 L 35 35 1 1 B
|
||||
X RTCX1 16 -1200 -1950 150 R 35 35 1 1 I
|
||||
X P3[26]/STCLK/MAT0[1]/PWM1[3] 26 1200 -1750 150 L 35 35 1 1 B
|
||||
X P1[22]/MCOB0/USB_PWRD/MAT1[0] 36 1200 850 150 L 35 35 1 1 B
|
||||
X P0[0]/RD1/TXD3/SDA1 46 -1200 1300 150 R 35 35 1 1 B
|
||||
X P0[22]/RTS1/TD1 56 -1200 -600 150 R 35 35 1 1 B
|
||||
X P2[7]/RD2/RTS1 66 1200 -950 150 L 35 35 1 1 B
|
||||
X P0[9]/I2STX_SDA/MOSI1/MAT2[3] 76 -1200 400 150 R 35 35 1 1 B
|
||||
X P1[17]/ENET_MDIO 86 1200 1350 150 L 35 35 1 1 B
|
||||
X VDD(3V3) 96 -100 2600 150 D 35 35 1 1 W
|
||||
X ~RESET~ 17 -1200 1650 150 R 35 35 1 1 I
|
||||
X P3[25]/MAT0[0]/PWM1[2] 27 1200 -1650 150 L 35 35 1 1 B
|
||||
X P1[23]/MCI1/PWM1[4]/MISO0 37 1200 750 150 L 35 35 1 1 B
|
||||
X P0[1]/TD1/RXD3/SCL1 47 -1200 1200 150 R 35 35 1 1 B
|
||||
X P0[21]/RI1/RD1 57 -1200 -500 150 R 35 35 1 1 B
|
||||
X P2[6]/PCAP1[0]/RI1/TRACECLK 67 1200 -850 150 L 35 35 1 1 B
|
||||
X P0[8]/I2STX_WS/MISO1/MAT2[2] 77 -1200 500 150 R 35 35 1 1 B
|
||||
X P1[16]/ENET_MDC 87 1200 1450 150 L 35 35 1 1 B
|
||||
X VSS 97 -100 -2700 150 U 35 35 1 1 W
|
||||
X RTCX2 18 -1200 -2100 150 R 35 35 1 1 O
|
||||
X VDD(3V3) 28 -400 2600 150 D 35 35 1 1 W
|
||||
X P1[24]/MCI2/PWM1[5]/MOSI0 38 1200 650 150 L 35 35 1 1 B
|
||||
X P0[10]/TXD2/SDA2/MAT3[0] 48 -1200 300 150 R 35 35 1 1 B
|
||||
X P0[20]/DTR1/SCL1 58 -1200 -400 150 R 35 35 1 1 B
|
||||
X P2[5]/PWM1[6]/DTR1/TRACEDATA[0] 68 1200 -750 150 L 35 35 1 1 B
|
||||
X P0[7]/I2STX_CLK/SCK1/MAT2[1] 78 -1200 600 150 R 35 35 1 1 B
|
||||
X P1[15]/ENET_REF_CLK 88 1200 1550 150 L 35 35 1 1 B
|
||||
X P0[2]/TXD0/AD0[7] 98 -1200 1100 150 R 35 35 1 1 B
|
||||
X VBAT 19 -1200 -2350 150 R 35 35 1 1 I
|
||||
X P0[29]/USB_D+ 29 -1200 -1300 150 R 35 35 1 1 B
|
||||
X P1[25]/MCOA1/MAT1[1] 39 1200 550 150 L 35 35 1 1 B
|
||||
X P0[11]/RXD2/SCL2/MAT3[1] 49 -1200 200 150 R 35 35 1 1 B
|
||||
X P0[19]/DSR1/SDA1 59 -1200 -300 150 R 35 35 1 1 B
|
||||
X P2[4]/PWM1[5]/DSR1/TRACEDATA[1] 69 1200 -650 150 L 35 35 1 1 B
|
||||
X P0[6]/I2SRX_SDA/SSEL1/MAT2[0] 79 -1200 700 150 R 35 35 1 1 B
|
||||
X P1[14]/ENET_RX_ER 89 1200 1650 150 L 35 35 1 1 B
|
||||
X P0[3]/RXD0/AD0[6] 99 -1200 1000 150 R 35 35 1 1 B
|
||||
X RTCK 100 -1200 2350 150 R 35 35 1 1 O
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# LPC2148
|
||||
#
|
||||
DEF LPC2148 U 0 40 Y Y 1 F N
|
||||
|
|
|
|||
Loading…
Reference in a new issue