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Fix PIC16F18325-I/SL violations of KLC 4.1

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This commit is contained in:
Antonio Vázquez 2017-07-23 12:16:48 +02:00
parent ee050c23f2
commit d2f3441424
1 changed files with 16 additions and 16 deletions
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32
library/microchip_pic16mcu.lib
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@ -3042,25 +3042,25 @@ ENDDEF
DEF PIC16F18325-I/SL U 0 40 Y Y 1 F N DEF PIC16F18325-I/SL U 0 40 Y Y 1 F N
F0 "U" -2300 600 50 H V L CNN F0 "U" -2300 600 50 H V L CNN
F1 "PIC16F18325-I/SL" -2300 500 50 H V L CNN F1 "PIC16F18325-I/SL" -2300 500 50 H V L CNN
F2 "Housings_SOIC:SOIC-14_3.9x8.7mm_Pitch1.27mm" 0 -700 50 H I C CNN F2 "Housings_SOIC:SOIC-14_3.9x8.7mm_Pitch1.27mm" 0 -600 50 H I C CNN
F3 "http://ww1.microchip.com/downloads/en/devicedoc/40001795b.pdf" 0 -800 50 H I C CNN F3 "http://ww1.microchip.com/downloads/en/devicedoc/40001795b.pdf" 0 -700 50 H I C CNN
ALIAS PIC16LF18325-I/SL ALIAS PIC16LF18325-I/SL
DRAW DRAW
S -2300 450 2300 -450 0 1 0 f S -2350 450 2350 -350 1 1 0 f
X VDD 1 0 600 150 D 50 50 1 1 W X VDD 1 0 600 150 D 50 50 1 1 W
X RA5/ANA5/T1CKI/SOSCIN/SOSCI/CLCIN3/CLKIN/OSC1 2 -2450 -250 150 R 50 50 1 1 B X RA5/ANA5/T1CKI/SOSCIN/SOSCI/CLCIN3/CLKIN/OSC1 2 -2500 -200 150 R 50 50 1 1 B
X RA4/ANA4/T1G/SOSCO/CLKOUT/OSC2 3 -2450 -150 150 R 50 50 1 1 B X RA4/ANA4/T1G/SOSCO/CLKOUT/OSC2 3 -2500 -100 150 R 50 50 1 1 B
X RA3/~MCLR~/VPP 4 -2450 -50 150 R 50 50 1 1 B X RA3/~MCLR~/VPP 4 -2500 0 150 R 50 50 1 1 B
X DT/RX/SDA2/SDI2/CCP1/T3CKI/MDCIN2/ANC5/RC5 5 2450 -250 150 L 50 50 1 1 B X DT/RX/SDA2/SDI2/CCP1/T3CKI/MDCIN2/ANC5/RC5 5 2500 -200 150 L 50 50 1 1 B
X CLCIN1/SCL2/SCK2/T3G/ANC4/RC4 6 2450 -150 150 L 50 50 1 1 B X CLCIN1/SCL2/SCK2/T3G/ANC4/RC4 6 2500 -100 150 L 50 50 1 1 B
X CLCIN0/~SS1~/CCP2/T5G/MDMIN/C2IN3-/C1IN3-/ANC3/RC3 7 2450 -50 150 L 50 50 1 1 B X CLCIN0/~SS1~/CCP2/T5G/MDMIN/C2IN3-/C1IN3-/ANC3/RC3 7 2500 0 150 L 50 50 1 1 B
X MDCIN1/C2IN2-/C1IN2-/ANC2/RC2 8 2450 50 150 L 50 50 1 1 B X MDCIN1/C2IN2-/C1IN2-/ANC2/RC2 8 2500 100 150 L 50 50 1 1 B
X CLCIN2/SDA1/SDI/CCP4/C2IN1-/C1IN1-/ANC1/RC1 9 2450 150 150 L 50 50 1 1 B X CLCIN2/SDA1/SDI/CCP4/C2IN1-/C1IN1-/ANC1/RC1 9 2500 200 150 L 50 50 1 1 B
X SCL1/SCK/T5CKI/C2IN0+/ANC0/RC0 10 2450 250 150 L 50 50 1 1 B X SCL1/SCK/T5CKI/C2IN0+/ANC0/RC0 10 2500 300 150 L 50 50 1 1 B
X RA2/ANA2/Vref-/DAC1Ref-/T0CKI/CCP3/CWG1IN/CWG2IN 11 -2450 50 150 R 50 50 1 1 B X RA2/ANA2/Vref-/DAC1Ref-/T0CKI/CCP3/CWG1IN/CWG2IN 11 -2500 100 150 R 50 50 1 1 B
X RA1/ANA1/Vref+/C1IN0-/C2IN0-/DAC1Ref+/ICSPCLK 12 -2450 150 150 R 50 50 1 1 B X RA1/ANA1/Vref+/C1IN0-/C2IN0-/DAC1Ref+/ICSPCLK 12 -2500 200 150 R 50 50 1 1 B
X RA0/ANA0/C1IN0+/DAC1OUT/~SS2~/ICSPDAT 13 -2450 250 150 R 50 50 1 1 B X RA0/ANA0/C1IN0+/DAC1OUT/~SS2~/ICSPDAT 13 -2500 300 150 R 50 50 1 1 B
X VSS 14 0 -600 150 U 50 50 1 1 W X VSS 14 0 -500 150 U 50 50 1 1 W
ENDDRAW ENDDRAW
ENDDEF ENDDEF
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