From cf7cd88aec82bb1e43f7796cd937940b6b5fc3f6 Mon Sep 17 00:00:00 2001
From: Scott <scott.gilliland@gatech.edu>
Date: Wed, 12 Aug 2015 12:31:14 -0400
Subject: [PATCH] Added a schematic symbol for the STM32F405Rx, which is the
 64-pin version of the 100-pin STM32F405Vx

---
 library/stm32.dcm |  6 ++++
 library/stm32.lib | 79 +++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 85 insertions(+)

diff --git a/library/stm32.dcm b/library/stm32.dcm
index 51cf2c25..6a240cbd 100644
--- a/library/stm32.dcm
+++ b/library/stm32.dcm
@@ -264,6 +264,12 @@ K STM32 ARM Cortex-M3 MCU
 F http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00220364.pdf
 $ENDCMP
 #
+$CMP STM32F405R
+D STM32F405Rx, 32-bit ARM Cortex-M4F microcontroller, 168 MHz, 512-1024 kB Flash, 192 kB SRAM, FPU
+K ARM 32bit CortexM4F M4F STM Microcontroller FPU
+F http://www.st.com/web/catalog/mmc/FM141/SC1169/SS1577/LN1035/PF252144
+$ENDCMP
+#
 $CMP STM32F405VG
 D STM32F407VG, 32-bit ARM Cortex-M4F microcontroller, 168 MHz, 1024 kB Flash, 192 kB SRAM, FPU
 K ARM 32bit CortexM4F M4F STM Microcontroller FPU
diff --git a/library/stm32.lib b/library/stm32.lib
index da555bd4..4e22c0ae 100644
--- a/library/stm32.lib
+++ b/library/stm32.lib
@@ -1639,6 +1639,85 @@ X VDD 100 100 2850 150 D 40 40 1 1 W
 ENDDRAW
 ENDDEF
 #
+# STM32F405R
+#
+DEF STM32F405R U 0 40 Y Y 1 F N
+F0 "U" 100 -550 60 H V C CNN
+F1 "STM32F405R" 100 -450 60 H V C CNN
+F2 "TQFP64" 100 -650 60 H V C CNN
+F3 "" 100 -550 60 H V C CNN
+$FPLIST
+ LQFP64
+$ENDFPLIST
+DRAW
+S -3300 -2100 3100 2000 0 1 0 f
+X VBAT 1 1000 2300 300 D 50 50 1 1 I
+X PC13/EVENTOUT 2 3400 -1500 300 L 50 50 1 1 I
+X PC14/OSC32_IN/EVENTOUT 3 3400 -1600 300 L 50 50 1 1 I
+X PC15/OSC32_OUT/EVENTOUT 4 3400 -1700 300 L 50 50 1 1 I
+X PH0/OSC_IN/EVENTOUT 5 -3600 1150 300 R 50 50 1 1 I
+X PH1/OSC_OUT/EVENTOUT 6 -3600 550 300 R 50 50 1 1 I
+X NRST 7 -3600 1350 300 R 50 50 1 1 I
+X PC0/OTG_HS_ULPI_STP/EVENTOUT 8 3400 -200 300 L 50 50 1 1 I
+X PC1/EVENTOUT 9 3400 -300 300 L 50 50 1 1 I
+X PC2/SPI2_MISO/OTG_HS_ULPI_DIR/I2S2ext_SD/EVENTOUT 10 3400 -400 300 L 50 50 1 1 I
+X PA4/SPI1_NSS/SPI3_NSS/USART2_CK/OTG_HS_SOF/I2S3_WS/EVENTOUT 20 -3600 -650 300 R 50 50 1 1 I
+X PB11/I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4/TIM2_CH4/EVENTOUT 30 3400 500 300 L 50 50 1 1 I
+X PC9/I2S_CKIN/MCO2/TIM8_CH4/SDIO_D1/I2C3_SDA/TIM3_CH4/EVENTOUT 40 3400 -1100 300 L 50 50 1 1 I
+X PA15/JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS/EVENTOUT 50 -3600 -1750 300 R 50 50 1 1 I
+X BOOT0 60 -3600 1550 300 R 50 50 1 1 I
+X PC3/SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT/EVENTOUT 11 3400 -500 300 L 50 50 1 1 I
+X PA5/SPI1_SCK/OTG_HS_ULPI_CK/TIM2_CH1_ETR/TIM8_CHIN/EVENTOUT 21 -3600 -750 300 R 50 50 1 1 I
+X VCAP_1 31 300 -2400 300 U 50 50 1 1 I
+X PA8/MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF/EVENTOUT 41 -3600 -1050 300 R 50 50 1 1 I
+X PC10/SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/USART3_TX/EVENTOUT 51 3400 -1200 300 L 50 50 1 1 I
+X PB8/TIM4_CH3/SDIO_D4/TIM10_CH1/I2C1_SCL/CAN1_RX/EVENTOUT 61 3400 800 300 L 50 50 1 1 I
+X VSSA 12 -1000 -2400 300 U 50 50 1 1 I
+X PA6/SPI1_MISO/TIM8_BKIN/TIM13_CH1/TIM3_CH1/TIM1_BKIN/EVENTOUT 22 -3600 -850 300 R 50 50 1 1 I
+X VDD 32 -100 2300 300 D 50 50 1 1 I
+X PA9/USART1_TX/TIM1_CH2/I2C3_SMBA/EVENTOUT 42 -3600 -1150 300 R 50 50 1 1 I
+X PC11/UART4_RX/SPI3_MISO/SDIO_D3/USART3_RX/I2S3ext_SD/EVENTOUT 52 3400 -1300 300 L 50 50 1 1 I
+X PB9/SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/I2C1_SDA/CAN1_TX/EVENTOUT 62 3400 700 300 L 50 50 1 1 I
+X VDDA 13 -900 2300 300 D 50 50 1 1 I
+X PA7/SPI1_MOSI/TIM8_CH1N/TIM14_CH1/TIM3_CH2/TIM1_CH1N/EVENTOUT 23 -3600 -950 300 R 50 50 1 1 I
+X PB12/SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN/CAN2_RX/OTG_HS_ULPI_D5/OTG_HS_ID/EVENTOUT 33 3400 400 300 L 50 50 1 1 I
+X PA10/USART1_RX/TIM1_CH3/OTG_FS_ID/EVENTOUT 43 -3600 -1250 300 R 50 50 1 1 I
+X PC12/UART5_TX/SDIO_CK/SPI3_MOSI/I2S3_SD/USART3_CK/EVENTOUT 53 3400 -1400 300 L 50 50 1 1 I
+X VSS 63 -600 -2400 300 U 50 50 1 1 I
+X PA0/WKUP/USART2_CTS/UART4_TX/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR/EVENTOUT 14 -3600 -250 300 R 50 50 1 1 I
+X PC4/EVENTOUT 24 3400 -600 300 L 50 50 1 1 I
+X PB13/SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N/CAN2_TX/OTG_HS_ULPI_D6/EVENTOUT 34 3400 300 300 L 50 50 1 1 I
+X PA11/USART1_CTS/CAN1_RX/TIM1_CH4_/OTG_FS_DM/EVENTOUT 44 -3600 -1350 300 R 50 50 1 1 I
+X PD2/TIM3_ETR/UART5_RX/SDIO_CMD/EVENTOUT 54 -3600 150 300 R 50 50 1 1 I
+X VDD 64 500 2300 300 D 50 50 1 1 I
+X PA1/USART2_RTS/UART4_RX/TIM5_CH2/TIMM2_CH2/EVENTOUT 15 -3600 -350 300 R 50 50 1 1 I
+X PC5/EVENTOUT 25 3400 -700 300 L 50 50 1 1 I
+X PB14/SPI2_MISO/TIM1_CH2N/TIM12_CH1/OTG_HS_DM/USART3_RTS/TIM8_CH2N/I2S2ext_SD/EVENTOUT 35 3400 200 300 L 50 50 1 1 I
+X PA12/USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP/EVENTOUT 45 -3600 -1450 300 R 50 50 1 1 I
+X PB3/JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK/EVENTOUT 55 3400 1300 300 L 50 50 1 1 I
+X PA2/USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3/EVENTOUT 16 -3600 -450 300 R 50 50 1 1 I
+X PB0/TIM3_CH3/TIM8_CH2N/OTG_HS_ULPI_D1/TIM1_CH2N/EVENTOUT 26 3400 1600 300 L 50 50 1 1 I
+X PB15/SPI2_MOSI/I2S2_SD/TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP/EVENTOUT 36 3400 100 300 L 50 50 1 1 I
+X PA13/JTMS/SWDIO/EVENTOUT 46 -3600 -1550 300 R 50 50 1 1 I
+X PB4/NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD/EVENTOUT 56 3400 1200 300 L 50 50 1 1 I
+X PA3/USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/OTG_HS_ULPI_D0/EVENTOUT 17 -3600 -550 300 R 50 50 1 1 I
+X PB1/TIM3_CH4/TIM8_CH3N/OTG_HS_ULPI_D2/OTG_HS_INTN/TIM1_CH3N/EVENTOUT 27 3400 1500 300 L 50 50 1 1 I
+X PC6/I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/TIM3_CH1/EVENTOUT 37 3400 -800 300 L 50 50 1 1 I
+X VCAP_2 47 800 -2400 300 U 50 50 1 1 I
+X PB5/I2C1_SMBA/CAN2_RX/OTG_HS_ULPI_D7/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/I2S3_SD/EVENTOUT 57 3400 1100 300 L 50 50 1 1 I
+X VSS 18 -800 -2400 300 U 50 50 1 1 I
+X PB2/BOOT1/EVENTOUT 28 3400 1400 300 L 50 50 1 1 I
+X PC7/I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/TIM3_CH2/EVENTOUT 38 3400 -900 300 L 50 50 1 1 I
+X VDD 48 200 2300 300 D 50 50 1 1 I
+X PB6/I2C1_SCL/TIM4_CH1/CAN2_TX/USART1_TX/EVENTOUT 58 3400 1000 300 L 50 50 1 1 I
+X VDD 19 -400 2300 300 D 50 50 1 1 I
+X PB10/SPI2_SCK/I2S2_CK/I2C2_SCL/USART3_TX/OTG_HS_ULPI_D3/TIM2_CH3/EVENTOUT 29 3400 600 300 L 50 50 1 1 I
+X PC8/TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK/EVENTOUT 39 3400 -1000 300 L 50 50 1 1 I
+X PA14/JTCK/SWCLK/EVENTOUT 49 -3600 -1650 300 R 50 50 1 1 I
+X PB7/I2C1_SDA/FSMC_NL/USART1_RX/TIM4_CH2/EVENTOUT 59 3400 900 300 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
 # STM32F405VG
 #
 DEF STM32F405VG U 0 40 Y Y 1 F N