Layout for DRV8308 IC

This commit is contained in:
Oliver Walters 2016-05-23 11:29:45 +10:00
parent 6b7b7b7be8
commit bc696de0c9
2 changed files with 35 additions and 35 deletions

View file

@ -13,7 +13,7 @@ F http://www.allegromicro.com/~/media/Files/Datasheets/A4950-Datasheet.ashx
$ENDCMP
#
$CMP DRV8308
D Brushless DC motor controller, closed loop, hall sensor inputs, current limiting, SPI configuration,
D Brushless DC motor controller, closed loop, hall sensor inputs, current limiting, SPI interface
K bldc mosfet-driver hall-sensor
F http://www.ti.com/lit/ds/symlink/drv8308.pdf
$ENDCMP

View file

@ -29,59 +29,59 @@ ENDDEF
# DRV8308
#
DEF DRV8308 U 0 40 Y Y 1 F N
F0 "U" -650 1450 50 H V C CNN
F1 "DRV8308" 550 1450 50 H V C CNN
F2 "Housings_DFN_QFN:QFN-40-1EP_6x6mm_Pitch0.5mm" 0 -1100 50 H I C CNN
F0 "U" -700 1450 50 H V L CNN
F1 "DRV8308" -700 -850 50 H V L CNN
F2 "Housings_DFN_QFN:QFN-40-1EP_6x6mm_Pitch0.5mm_TI_PVQFN-N40" 50 -1000 50 H I C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
QFN*1EP*6x6mm*Pitch0.5mm*
$ENDFPLIST
DRAW
T 0 450 -100 50 0 0 0 Hall~Sensors Normal 0 R C
T 0 450 1100 50 0 0 0 Phase~U Normal 0 R C
T 0 450 700 50 0 0 0 Phase~V Normal 0 R C
T 0 450 300 50 0 0 0 Phase~W Normal 0 R C
S -700 1400 700 -700 0 1 10 f
X UHP 1 800 -100 100 L 50 50 1 1 I
X UHN 2 800 -200 100 L 50 50 1 1 I
X VHP 3 800 -300 100 L 50 50 1 1 I
X VHN 4 800 -400 100 L 50 50 1 1 I
X WHP 5 800 -500 100 L 50 50 1 1 I
X WHN 6 800 -600 100 L 50 50 1 1 I
T 0 650 -100 50 0 0 0 Hall~Sensors Normal 0 R C
T 0 675 1000 50 0 0 0 Phase~U Normal 0 R C
T 0 675 600 50 0 0 0 Phase~V Normal 0 R C
T 0 675 200 50 0 0 0 Phase~W Normal 0 R C
S -700 1400 700 -800 0 1 10 f
X UHP 1 800 -200 100 L 50 50 1 1 I
X UHN 2 800 -300 100 L 50 50 1 1 I
X VHP 3 800 -400 100 L 50 50 1 1 I
X VHN 4 800 -500 100 L 50 50 1 1 I
X WHP 5 800 -600 100 L 50 50 1 1 I
X WHN 6 800 -700 100 L 50 50 1 1 I
X VSW 7 100 1500 100 D 50 50 1 1 w
X FBFB 8 1850 1250 100 L 50 50 1 1 O
X FGINN_TACH 9 1850 1000 100 L 50 50 1 1 I
X FGINP 10 1850 900 100 L 50 50 1 1 B
X BRAKE 20 -800 100 100 R 50 50 1 1 I
X FGFB 8 -800 -200 100 R 50 50 1 1 O
X FGINN_TACH 9 -800 -300 100 R 50 50 1 1 I
X FGINP 10 -800 -400 100 R 50 50 1 1 B
X BRAKE 20 -800 300 100 R 50 50 1 1 I
X CP1 30 -800 1300 100 R 50 50 1 1 P
X WLSG 40 800 300 100 L 50 50 1 1 O
X SCLK 11 -800 800 100 R 50 50 1 1 I
X DIR 21 -800 -100 100 R 50 50 1 1 I
X ISEN 31 800 100 100 L 50 50 1 1 I
X GND 41 100 -800 100 U 50 50 1 1 W
X SCS 12 -800 700 100 R 50 50 1 1 I
X ENABLE 22 -800 -200 100 R 50 50 1 1 I
X SCLK 11 -800 1000 100 R 50 50 1 1 I
X DIR 21 -800 100 100 R 50 50 1 1 I
X ISEN 31 800 0 100 L 50 50 1 1 I
X GND 41 100 -900 100 U 50 50 1 1 W
X SCS 12 -800 900 100 R 50 50 1 1 I
X ENABLE 22 -800 0 100 R 50 50 1 1 I
X UHSG 32 800 1300 100 L 50 50 1 1 O
X SMODE 13 -800 400 100 R 50 50 1 1 I
X RESET 23 -800 200 100 R 50 50 1 1 I
X SMODE 13 -800 600 100 R 50 50 1 1 I
X RESET 23 -800 400 100 R 50 50 1 1 I
X U 33 800 1200 100 L 50 50 1 1 I
X SDATAI 14 -800 600 100 R 50 50 1 1 I
X SDATAI 14 -800 800 100 R 50 50 1 1 I
X VREG 24 200 1500 100 D 50 50 1 1 w
X ULSG 34 800 1100 100 L 50 50 1 1 O
X SDATAO 15 -800 500 100 R 50 50 1 1 O
X VINT 25 -400 1500 100 D 50 50 1 1 P
X SDATAO 15 -800 700 100 R 50 50 1 1 O
X VINT 25 -300 1500 100 D 50 50 1 1 P
X VHSG 35 800 900 100 L 50 50 1 1 O
X FGOUT 16 -800 -500 100 R 50 50 1 1 O
X GND 26 -100 -800 100 U 50 50 1 1 W
X GND 26 -100 -900 100 U 50 50 1 1 W
X V 36 800 800 100 L 50 50 1 1 I
X ~FAULTn 17 -800 -400 100 R 50 50 1 1 O
X ~FAULTn 17 -800 -600 100 R 50 50 1 1 O
X VM 27 0 1500 100 D 50 50 1 1 W
X VLSG 37 800 700 100 L 50 50 1 1 O
X ~LOCKn 18 -800 -600 100 R 50 50 1 1 O
X ~LOCKn 18 -800 -700 100 R 50 50 1 1 O
X VCP 28 -200 1500 100 D 50 50 1 1 P
X WHSG 38 800 500 100 L 50 50 1 1 O
X CLKIN 19 -800 0 100 R 50 50 1 1 I
X CP2 29 -800 1100 100 R 50 50 1 1 P
X CLKIN 19 -800 200 100 R 50 50 1 1 I
X CP2 29 -800 1200 100 R 50 50 1 1 P
X W 39 800 400 100 L 50 50 1 1 I
ENDDRAW
ENDDEF