From 16ee671e6b14b6c4ad9835d43b3f81bb63367c5d Mon Sep 17 00:00:00 2001
From: jkriege2 <jan@jkrieger.de>
Date: Tue, 20 Dec 2016 21:51:24 +0100
Subject: [PATCH 1/9] renamed 3D package lib to Relays_THT.3dshapes to conform
 to Relays_THT.pretty and this PR:
 https://github.com/KiCad/Relays_THT.pretty/pull/13/files

---
 .../Relay_DPDT_IM0(3,6,7)NS.wrl                     |   0
 .../Relay_SANYOU_SRD_Series_Form_C.wings            | Bin
 .../Relay_SANYOU_SRD_Series_Form_C.wrl              |   0
 .../Relay_SPDS_OMRON-G6E.wings                      | Bin
 .../Relay_SPDS_OMRON-G6E.wrl                        |   0
 ..._SPDT_SingleRow_Laying_FinderType34Point51.wings | Bin
 ...ay_SPDT_SingleRow_Laying_FinderType34Point51.wrl |   0
 ...PDT_SingleRow_Standing_FinderType34Point51.wings | Bin
 ..._SPDT_SingleRow_Standing_FinderType34Point51.wrl |   0
 .../Relay_SPST_Schrack-RP-3SL_bistable.wings        | Bin
 .../Relay_SPST_Schrack-RP-3SL_bistable.wrl          |   0
 .../Relay_SPST_Schrack-RP-3SL_mono.wings            | Bin
 .../Relay_SPST_Schrack-RP-3SL_mono.wrl              |   0
 13 files changed, 0 insertions(+), 0 deletions(-)
 rename modules/packages3d/{Relays_ThroughHole.3dshapes => Relays_THT.3dshapes}/Relay_DPDT_IM0(3,6,7)NS.wrl (100%)
 rename modules/packages3d/{Relays_ThroughHole.3dshapes => Relays_THT.3dshapes}/Relay_SANYOU_SRD_Series_Form_C.wings (100%)
 rename modules/packages3d/{Relays_ThroughHole.3dshapes => Relays_THT.3dshapes}/Relay_SANYOU_SRD_Series_Form_C.wrl (100%)
 rename modules/packages3d/{Relays_ThroughHole.3dshapes => Relays_THT.3dshapes}/Relay_SPDS_OMRON-G6E.wings (100%)
 rename modules/packages3d/{Relays_ThroughHole.3dshapes => Relays_THT.3dshapes}/Relay_SPDS_OMRON-G6E.wrl (100%)
 rename modules/packages3d/{Relays_ThroughHole.3dshapes => Relays_THT.3dshapes}/Relay_SPDT_SingleRow_Laying_FinderType34Point51.wings (100%)
 rename modules/packages3d/{Relays_ThroughHole.3dshapes => Relays_THT.3dshapes}/Relay_SPDT_SingleRow_Laying_FinderType34Point51.wrl (100%)
 rename modules/packages3d/{Relays_ThroughHole.3dshapes => Relays_THT.3dshapes}/Relay_SPDT_SingleRow_Standing_FinderType34Point51.wings (100%)
 rename modules/packages3d/{Relays_ThroughHole.3dshapes => Relays_THT.3dshapes}/Relay_SPDT_SingleRow_Standing_FinderType34Point51.wrl (100%)
 rename modules/packages3d/{Relays_ThroughHole.3dshapes => Relays_THT.3dshapes}/Relay_SPST_Schrack-RP-3SL_bistable.wings (100%)
 rename modules/packages3d/{Relays_ThroughHole.3dshapes => Relays_THT.3dshapes}/Relay_SPST_Schrack-RP-3SL_bistable.wrl (100%)
 rename modules/packages3d/{Relays_ThroughHole.3dshapes => Relays_THT.3dshapes}/Relay_SPST_Schrack-RP-3SL_mono.wings (100%)
 rename modules/packages3d/{Relays_ThroughHole.3dshapes => Relays_THT.3dshapes}/Relay_SPST_Schrack-RP-3SL_mono.wrl (100%)

diff --git a/modules/packages3d/Relays_ThroughHole.3dshapes/Relay_DPDT_IM0(3,6,7)NS.wrl b/modules/packages3d/Relays_THT.3dshapes/Relay_DPDT_IM0(3,6,7)NS.wrl
similarity index 100%
rename from modules/packages3d/Relays_ThroughHole.3dshapes/Relay_DPDT_IM0(3,6,7)NS.wrl
rename to modules/packages3d/Relays_THT.3dshapes/Relay_DPDT_IM0(3,6,7)NS.wrl
diff --git a/modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SANYOU_SRD_Series_Form_C.wings b/modules/packages3d/Relays_THT.3dshapes/Relay_SANYOU_SRD_Series_Form_C.wings
similarity index 100%
rename from modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SANYOU_SRD_Series_Form_C.wings
rename to modules/packages3d/Relays_THT.3dshapes/Relay_SANYOU_SRD_Series_Form_C.wings
diff --git a/modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SANYOU_SRD_Series_Form_C.wrl b/modules/packages3d/Relays_THT.3dshapes/Relay_SANYOU_SRD_Series_Form_C.wrl
similarity index 100%
rename from modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SANYOU_SRD_Series_Form_C.wrl
rename to modules/packages3d/Relays_THT.3dshapes/Relay_SANYOU_SRD_Series_Form_C.wrl
diff --git a/modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPDS_OMRON-G6E.wings b/modules/packages3d/Relays_THT.3dshapes/Relay_SPDS_OMRON-G6E.wings
similarity index 100%
rename from modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPDS_OMRON-G6E.wings
rename to modules/packages3d/Relays_THT.3dshapes/Relay_SPDS_OMRON-G6E.wings
diff --git a/modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPDS_OMRON-G6E.wrl b/modules/packages3d/Relays_THT.3dshapes/Relay_SPDS_OMRON-G6E.wrl
similarity index 100%
rename from modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPDS_OMRON-G6E.wrl
rename to modules/packages3d/Relays_THT.3dshapes/Relay_SPDS_OMRON-G6E.wrl
diff --git a/modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPDT_SingleRow_Laying_FinderType34Point51.wings b/modules/packages3d/Relays_THT.3dshapes/Relay_SPDT_SingleRow_Laying_FinderType34Point51.wings
similarity index 100%
rename from modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPDT_SingleRow_Laying_FinderType34Point51.wings
rename to modules/packages3d/Relays_THT.3dshapes/Relay_SPDT_SingleRow_Laying_FinderType34Point51.wings
diff --git a/modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPDT_SingleRow_Laying_FinderType34Point51.wrl b/modules/packages3d/Relays_THT.3dshapes/Relay_SPDT_SingleRow_Laying_FinderType34Point51.wrl
similarity index 100%
rename from modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPDT_SingleRow_Laying_FinderType34Point51.wrl
rename to modules/packages3d/Relays_THT.3dshapes/Relay_SPDT_SingleRow_Laying_FinderType34Point51.wrl
diff --git a/modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPDT_SingleRow_Standing_FinderType34Point51.wings b/modules/packages3d/Relays_THT.3dshapes/Relay_SPDT_SingleRow_Standing_FinderType34Point51.wings
similarity index 100%
rename from modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPDT_SingleRow_Standing_FinderType34Point51.wings
rename to modules/packages3d/Relays_THT.3dshapes/Relay_SPDT_SingleRow_Standing_FinderType34Point51.wings
diff --git a/modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPDT_SingleRow_Standing_FinderType34Point51.wrl b/modules/packages3d/Relays_THT.3dshapes/Relay_SPDT_SingleRow_Standing_FinderType34Point51.wrl
similarity index 100%
rename from modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPDT_SingleRow_Standing_FinderType34Point51.wrl
rename to modules/packages3d/Relays_THT.3dshapes/Relay_SPDT_SingleRow_Standing_FinderType34Point51.wrl
diff --git a/modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPST_Schrack-RP-3SL_bistable.wings b/modules/packages3d/Relays_THT.3dshapes/Relay_SPST_Schrack-RP-3SL_bistable.wings
similarity index 100%
rename from modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPST_Schrack-RP-3SL_bistable.wings
rename to modules/packages3d/Relays_THT.3dshapes/Relay_SPST_Schrack-RP-3SL_bistable.wings
diff --git a/modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPST_Schrack-RP-3SL_bistable.wrl b/modules/packages3d/Relays_THT.3dshapes/Relay_SPST_Schrack-RP-3SL_bistable.wrl
similarity index 100%
rename from modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPST_Schrack-RP-3SL_bistable.wrl
rename to modules/packages3d/Relays_THT.3dshapes/Relay_SPST_Schrack-RP-3SL_bistable.wrl
diff --git a/modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPST_Schrack-RP-3SL_mono.wings b/modules/packages3d/Relays_THT.3dshapes/Relay_SPST_Schrack-RP-3SL_mono.wings
similarity index 100%
rename from modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPST_Schrack-RP-3SL_mono.wings
rename to modules/packages3d/Relays_THT.3dshapes/Relay_SPST_Schrack-RP-3SL_mono.wings
diff --git a/modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPST_Schrack-RP-3SL_mono.wrl b/modules/packages3d/Relays_THT.3dshapes/Relay_SPST_Schrack-RP-3SL_mono.wrl
similarity index 100%
rename from modules/packages3d/Relays_ThroughHole.3dshapes/Relay_SPST_Schrack-RP-3SL_mono.wrl
rename to modules/packages3d/Relays_THT.3dshapes/Relay_SPST_Schrack-RP-3SL_mono.wrl

From b458a196d1b80f3f85cd84190c412321da9658cb Mon Sep 17 00:00:00 2001
From: evanshultz <evanshultz@users.noreply.github.com>
Date: Tue, 28 Feb 2017 23:46:48 -0800
Subject: [PATCH 2/9] Create intersil.lib

---
 library/intersil.lib | 187 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 187 insertions(+)
 create mode 100644 library/intersil.lib

diff --git a/library/intersil.lib b/library/intersil.lib
new file mode 100644
index 00000000..c7d80091
--- /dev/null
+++ b/library/intersil.lib
@@ -0,0 +1,187 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# HIP2100_DFN
+#
+DEF HIP2100_DFN U 0 40 Y Y 1 F N
+F0 "U" 0 525 50 H V C CNN
+F1 "HIP2100_DFN" 0 450 50 H V C CNN
+F2 "Housings_DFN_QFN:DFN-12-1EP_4x4mm_Pitch0.5mm" 0 0 50 H I C CIN
+F3 "" 0 -550 50 H I C CNN
+ALIAS HIP2101_DFN
+$FPLIST
+ DFN*1EP*4x4mm*Pitch0.5mm*
+$ENDFPLIST
+DRAW
+S -200 -400 200 400 0 1 10 f
+X VDD 1 -300 300 100 R 50 50 1 1 W
+X NC 2 -300 200 100 R 50 50 1 1 N N
+X NC 3 -300 100 100 R 50 50 1 1 N N
+X HB 4 300 300 100 L 50 50 1 1 W
+X HO 5 300 -100 100 L 50 50 1 1 O
+X HS 6 300 -200 100 L 50 50 1 1 P
+X HI 7 -300 -100 100 R 50 50 1 1 I
+X LI 8 -300 -200 100 R 50 50 1 1 I
+X NC 9 300 200 100 L 50 50 1 1 N N
+X NC 10 300 100 100 L 50 50 1 1 N N
+X VSS 11 -300 -300 100 R 50 50 1 1 W
+X LO 12 300 -300 100 L 50 50 1 1 O
+X EP 13 0 -500 100 U 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# HIP2100_EPSOIC
+#
+DEF HIP2100_EPSOIC U 0 40 Y Y 1 F N
+F0 "U" 0 525 50 H V C CNN
+F1 "HIP2100_EPSOIC" 0 450 50 H V C CNN
+F2 "Housings_SOIC:SOIC-8-1EP_3.9x4.9mm_Pitch1.27mm" 0 0 50 H I C CIN
+F3 "" 0 -550 50 H I C CNN
+ALIAS HIP2101_EPSOIC
+$FPLIST
+ SOIC*1EP*3.9x4.9mm*Pitch1.27mm*
+$ENDFPLIST
+DRAW
+S -200 -400 200 400 0 1 10 f
+X VDD 1 -300 300 100 R 50 50 1 1 W
+X HB 2 300 300 100 L 50 50 1 1 W
+X HO 3 300 -100 100 L 50 50 1 1 O
+X HS 4 300 -200 100 L 50 50 1 1 P
+X HI 5 -300 -100 100 R 50 50 1 1 I
+X LI 6 -300 -200 100 R 50 50 1 1 I
+X VSS 7 -300 -300 100 R 50 50 1 1 W
+X LO 8 300 -300 100 L 50 50 1 1 O
+X EP 9 0 -500 100 U 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# HIP2100_QFN
+#
+DEF HIP2100_QFN U 0 40 Y Y 1 F N
+F0 "U" 0 525 50 H V C CNN
+F1 "HIP2100_QFN" 0 450 50 H V C CNN
+F2 "Housings_DFN_QFN:QFN-16-1EP_5x5mm_Pitch0.8mm" 0 0 50 H I C CIN
+F3 "" 0 -550 50 H I C CNN
+ALIAS HIP2101_QFN
+$FPLIST
+ QFN*1EP*5x5mm*Pitch0.8mm*
+$ENDFPLIST
+DRAW
+S -200 -400 200 400 0 1 10 f
+X NC 1 -300 200 100 R 50 50 1 1 N N
+X HB 2 300 300 100 L 50 50 1 1 W
+X HO 3 300 -100 100 L 50 50 1 1 O
+X NC 4 -300 100 100 R 50 50 1 1 N N
+X NC 5 -300 0 100 R 50 50 1 1 N N
+X HS 6 300 -200 100 L 50 50 1 1 P
+X HI 7 -300 -100 100 R 50 50 1 1 I
+X NC 8 -300 -400 100 R 50 50 1 1 N N
+X NC 9 300 200 100 L 50 50 1 1 N N
+X LI 10 -300 -200 100 R 50 50 1 1 I
+X VSS 11 -300 -300 100 R 50 50 1 1 W
+X NC 12 300 100 100 L 50 50 1 1 N N
+X NC 13 300 0 100 L 50 50 1 1 N N
+X LO 14 300 -300 100 L 50 50 1 1 O
+X NC 15 300 -400 100 L 50 50 1 1 N N
+X VDD 16 -300 300 100 R 50 50 1 1 W
+X EP 17 0 -500 100 U 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# HIP2100_SOIC
+#
+DEF HIP2100_SOIC U 0 40 Y Y 1 F N
+F0 "U" 0 525 50 H V C CNN
+F1 "HIP2100_SOIC" 0 450 50 H V C CNN
+F2 "Housings_SOIC:SOIC-8_3.9x4.9mm_Pitch1.27mm" 0 0 50 H I C CIN
+F3 "" 0 -550 50 H I C CNN
+ALIAS HIP2101_SOIC
+$FPLIST
+ SOIC*3.9x4.9mm*Pitch1.27mm*
+$ENDFPLIST
+DRAW
+S -200 -400 200 400 0 1 10 f
+X VDD 1 -300 300 100 R 50 50 1 1 W
+X HB 2 300 300 100 L 50 50 1 1 W
+X HO 3 300 -100 100 L 50 50 1 1 O
+X HS 4 300 -200 100 L 50 50 1 1 P
+X HI 5 -300 -100 100 R 50 50 1 1 I
+X LI 6 -300 -200 100 R 50 50 1 1 I
+X VSS 7 -300 -300 100 R 50 50 1 1 W
+X LO 8 300 -300 100 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# HIP4080A
+#
+DEF HIP4080A U 0 40 Y Y 1 F N
+F0 "U" 200 850 50 H V L CNN
+F1 "HIP4080A" 200 750 50 H V L CNN
+F2 "" -50 150 50 H I C CIN
+F3 "" -50 -400 50 H I C CNN
+$FPLIST
+ SOIC*7.5x12.8mm*Pitch1.27mm*
+ DIP*W7.62mm*
+$ENDFPLIST
+DRAW
+S -400 -700 400 700 0 1 10 f
+X BHB 1 500 600 100 L 50 50 1 1 I
+X HEN 2 -500 600 100 R 50 50 1 1 O
+X DIS 3 -500 500 100 R 50 50 1 1 O
+X VSS 4 0 -800 100 U 50 50 1 1 W
+X OUT 5 -500 200 100 R 50 50 1 1 O
+X IN+ 6 -500 -200 100 R 50 50 1 1 I
+X IN- 7 -500 -300 100 R 50 50 1 1 I
+X HDEL 8 -500 -500 100 R 50 50 1 1 P
+X LDEL 9 -500 -600 100 R 50 50 1 1 P
+X AHB 10 500 500 100 L 50 50 1 1 I
+X BHO 20 500 200 100 L 50 50 1 1 O
+X AHO 11 500 -600 100 L 50 50 1 1 O
+X AHS 12 500 -500 100 L 50 50 1 1 P
+X ALO 13 500 -400 100 L 50 50 1 1 O
+X ALS 14 500 -300 100 L 50 50 1 1 P
+X VCC 15 -100 800 100 D 50 50 1 1 W
+X VDD 16 100 800 100 D 50 50 1 1 W
+X BLS 17 500 -100 100 L 50 50 1 1 P
+X BLO 18 500 0 100 L 50 50 1 1 O
+X BHS 19 500 100 100 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# HIP4081A
+#
+DEF HIP4081A U 0 40 Y Y 1 F N
+F0 "U" 200 850 50 H V L CNN
+F1 "HIP4081A" 200 750 50 H V L CNN
+F2 "" -50 150 50 H I C CIN
+F3 "" -50 -400 50 H I C CNN
+$FPLIST
+ SOIC*7.5x12.8mm*Pitch1.27mm*
+ DIP*W7.62mm*
+$ENDFPLIST
+DRAW
+S -400 -700 400 700 0 1 10 f
+X BHB 1 500 600 100 L 50 50 1 1 I
+X BHI 2 -500 0 100 R 50 50 1 1 I
+X DIS 3 -500 600 100 R 50 50 1 1 O
+X VSS 4 0 -800 100 U 50 50 1 1 W
+X BLI 5 -500 -100 100 R 50 50 1 1 I
+X ALI 6 -500 100 100 R 50 50 1 1 I
+X AHI 7 -500 200 100 R 50 50 1 1 I
+X HDEL 8 -500 -500 100 R 50 50 1 1 P
+X LDEL 9 -500 -600 100 R 50 50 1 1 P
+X AHB 10 500 500 100 L 50 50 1 1 I
+X BHO 20 500 200 100 L 50 50 1 1 O
+X AHO 11 500 -600 100 L 50 50 1 1 O
+X AHS 12 500 -500 100 L 50 50 1 1 P
+X ALO 13 500 -400 100 L 50 50 1 1 O
+X ALS 14 500 -300 100 L 50 50 1 1 P
+X VCC 15 -100 800 100 D 50 50 1 1 W
+X VDD 16 100 800 100 D 50 50 1 1 W
+X BLS 17 500 -100 100 L 50 50 1 1 P
+X BLO 18 500 0 100 L 50 50 1 1 O
+X BHS 19 500 100 100 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library

From f1b74c8eb1d98d7e83032f1f4cbe68fac1574ba4 Mon Sep 17 00:00:00 2001
From: evanshultz <evanshultz@users.noreply.github.com>
Date: Tue, 28 Feb 2017 23:48:17 -0800
Subject: [PATCH 3/9] Create intersil.dcm

---
 library/intersil.dcm | 63 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 library/intersil.dcm

diff --git a/library/intersil.dcm b/library/intersil.dcm
new file mode 100644
index 00000000..40b756ad
--- /dev/null
+++ b/library/intersil.dcm
@@ -0,0 +1,63 @@
+EESchema-DOCLIB  Version 2.0
+#
+$CMP HIP2100_DFN
+D High Frequency Half Bridge Driver, Output Current 2.0A, 100V, DFN-8 4x4mm
+K Half Bridge Gate Driver
+F http://www.intersil.com/content/dam/Intersil/documents/hip2/hip2100.pdf
+$ENDCMP
+#
+$CMP HIP2100_EPSOIC
+D High Frequency Half Bridge Driver, Output Current 2.0A, 100V, EPSOIC-8
+K Half Bridge Gate Driver
+F http://www.intersil.com/content/dam/Intersil/documents/hip2/hip2100.pdf
+$ENDCMP
+#
+$CMP HIP2100_QFN
+D High Frequency Half Bridge Driver, Output Current 2.0A, 100V, QFN-16 5x5mm
+K Half Bridge Gate Driver
+F http://www.intersil.com/content/dam/Intersil/documents/hip2/hip2100.pdf
+$ENDCMP
+#
+$CMP HIP2100_SOIC
+D High Frequency Half Bridge Driver, Output Current 2.0A, 100V, SOIC-8
+K Half Bridge Gate Driver
+F http://www.intersil.com/content/dam/Intersil/documents/hip2/hip2100.pdf
+$ENDCMP
+#
+$CMP HIP2101_DFN
+D High Frequency Half Bridge Driver, TTL/CMOS inputs, Output Current 2.0A, 100V, DFN-8 4x4mm
+K Half Bridge Gate Driver
+F http://www.intersil.com/content/dam/Intersil/documents/hip2/hip2101.pdf
+$ENDCMP
+#
+$CMP HIP2101_EPSOIC
+D High Frequency Half Bridge Driver, TTL/CMOS inputs, Output Current 2.0A, 100V, EPSOIC-8
+K Half Bridge Gate Driver
+F http://www.intersil.com/content/dam/Intersil/documents/hip2/hip2101.pdf
+$ENDCMP
+#
+$CMP HIP2101_QFN
+D High Frequency Half Bridge Driver, TTL/CMOS inputs, Output Current 2.0A, 100V, QFN-16 5x5mm
+K Half Bridge Gate Driver
+F http://www.intersil.com/content/dam/Intersil/documents/hip2/hip2101.pdf
+$ENDCMP
+#
+$CMP HIP2101_SOIC
+D High Frequency Half Bridge Driver, TTL/CMOS inputs, Output Current 2.0A, 100V, SOIC-8
+K Half Bridge Gate Driver
+F http://www.intersil.com/content/dam/Intersil/documents/hip2/hip2101.pdf
+$ENDCMP
+#
+$CMP HIP4080A
+D High Frequency Full Bridge FET Driver, Input Comparator, 2.5A, 80V
+K Half Bridge Gate Driver
+F http://www.intersil.com/content/dam/Intersil/documents/hip4/hip4080a.pdf
+$ENDCMP
+#
+$CMP HIP4081A
+D High Frequency Full Bridge FET Driver, 2.5A, 80V
+K Half Bridge Gate Driver
+F http://www.intersil.com/content/dam/Intersil/documents/hip4/hip4080a.pdf
+$ENDCMP
+#
+#End Doc Library

From 077084ff1757656f44731c635b014b4a22ecf481 Mon Sep 17 00:00:00 2001
From: Andrew Bradford <andrew@bradfordembedded.com>
Date: Tue, 7 Feb 2017 06:30:39 -0500
Subject: [PATCH 4/9] silabs: Create CP2102N-A01-GQFN24 symbol

CP2102N family are USB to UART bridges in various QFN packages.

Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
---
 library/silabs.dcm |  6 ++++++
 library/silabs.lib | 40 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 46 insertions(+)

diff --git a/library/silabs.dcm b/library/silabs.dcm
index 2b699bde..f950adfe 100644
--- a/library/silabs.dcm
+++ b/library/silabs.dcm
@@ -1,5 +1,11 @@
 EESchema-DOCLIB  Version 2.0
 #
+$CMP CP2102N-A01-GQFN24
+D USB to UART master bridge
+K USB UART bridge
+F http://www.silabs.com/support%20documents/technicaldocs/cp2102n-datasheet.pdf
+$ENDCMP
+#
 $CMP CP2104
 D Single-Chip USB-to-UART Bridge, USB 2.0 Full-Speed, 2Mbps UART, QFN package
 K uart usb bridge interface transceiver
diff --git a/library/silabs.lib b/library/silabs.lib
index 41f17242..083bd533 100644
--- a/library/silabs.lib
+++ b/library/silabs.lib
@@ -1,6 +1,46 @@
 EESchema-LIBRARY Version 2.3
 #encoding utf-8
 #
+# CP2102N-A01-GQFN24
+#
+DEF CP2102N-A01-GQFN24 U 0 40 Y Y 1 F N
+F0 "U" -400 800 50 H V C CNN
+F1 "CP2102N-A01-GQFN24" -550 -800 50 H V C CNN
+F2 "Housings_DFN_QFN:QFN-24-1EP_4x4mm_Pitch0.5mm" 50 -1050 50 H I C CNN
+F3 "" 50 -1050 50 H I C CNN
+$FPLIST
+ QFN*4x4mm*Pitch0.5mm*
+$ENDFPLIST
+DRAW
+S -450 750 450 -750 0 1 10 f
+X RI/CLK 1 600 600 150 L 50 50 1 1 B
+X GND 2 100 -900 150 U 50 50 1 1 W
+X D+ 3 -600 -400 150 R 50 50 1 1 B
+X D- 4 -600 -500 150 R 50 50 1 1 B
+X VIO 5 0 900 150 D 50 50 1 1 W
+X VDD 6 -100 900 150 D 50 50 1 1 W
+X REGIN 7 -600 0 150 R 50 50 1 1 W
+X VBUS 8 -600 -300 150 R 50 50 1 1 I
+X ~RSTb 9 -600 600 150 R 50 50 1 1 I
+X NC 10 400 -900 150 U 50 50 1 1 N N
+X RXD 20 600 300 150 L 50 50 1 1 I
+X GPIO.3 11 600 -300 150 L 50 50 1 1 B
+X TXD 21 600 200 150 L 50 50 1 1 O
+X GPIO.2 12 600 -400 150 L 50 50 1 1 B
+X DSR 22 600 100 150 L 50 50 1 1 I
+X GPIO.1 13 600 -500 150 L 50 50 1 1 B
+X DTR 23 600 0 150 L 50 50 1 1 O
+X GPIO.0 14 600 -600 150 L 50 50 1 1 B
+X DCD 24 600 -100 150 L 50 50 1 1 I
+X ~SUSPENDb 15 -600 200 150 R 50 50 1 1 O
+X GND 25 0 -900 150 U 50 50 1 1 W
+X NC 16 300 -900 150 U 50 50 1 1 N N
+X SUSPEND 17 -600 300 150 R 50 50 1 1 O
+X CTS 18 600 500 150 L 50 50 1 1 I
+X RTS 19 600 400 150 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
 # CP2104
 #
 DEF CP2104 U 0 40 Y Y 1 F N

From a011a01397731b4e890cbc6d900ed10cbd09f60e Mon Sep 17 00:00:00 2001
From: Andrew Bradford <andrew@bradfordembedded.com>
Date: Sat, 4 Mar 2017 13:16:46 -0500
Subject: [PATCH 5/9] silabs: CP2112: fix KLC violations

Switched VBUS to be an input pin, both suspend pins to be outputs, and
all GND pins to be power inputs as per the CP2112 datasheet.

Prior to fixing, KLC violations were:
checking component: CP2112
  Violating Rule 3.9
    For components with a single default footprint, footprint field is filled with valid footprint
    filename
  Violating EC01 - Extra Checking
    Check pins names against pin types.
  Violating EC03 - Extra Checking
    Check part reference, name and footprint position and alignment
  Violating EC04 - Extra Checking
    Check line width and background for box outlines parts.

Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
---
 library/silabs.lib | 19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/library/silabs.lib b/library/silabs.lib
index 083bd533..4c26c894 100644
--- a/library/silabs.lib
+++ b/library/silabs.lib
@@ -84,12 +84,15 @@ ENDDEF
 # CP2112
 #
 DEF CP2112 U 0 40 Y Y 1 F N
-F0 "U" -400 700 50 H V C CNN
-F1 "CP2112" -300 -700 50 H V C CNN
-F2 "QFN-24-1EP_4x4mm_Pitch0.5mm" 50 -1000 50 H I C CNN
+F0 "U" -100 775 50 H V R CNN
+F1 "CP2112" -100 700 50 H V R CNN
+F2 "Housings_DFN_QFN:QFN-24-1EP_4x4mm_Pitch0.5mm" 450 -700 50 H I L CNN
 F3 "" 50 -1000 50 H I C CNN
+$FPLIST
+ QFN*4x4mm*Pitch0.5mm*
+$ENDFPLIST
 DRAW
-S -450 650 450 -650 0 1 0 f
+S -450 650 450 -650 0 1 10 f
 X SDA 1 600 500 150 L 50 50 1 1 B
 X GND 2 100 -800 150 U 50 50 1 1 W
 X D+ 3 -600 -400 150 R 50 50 1 1 B
@@ -97,11 +100,11 @@ X D- 4 -600 -500 150 R 50 50 1 1 B
 X VIO 5 100 800 150 D 50 50 1 1 W
 X VDD 6 0 800 150 D 50 50 1 1 W
 X REGIN 7 -600 -100 150 R 50 50 1 1 W
-X VBUS 8 -600 -300 150 R 50 50 1 1 O
+X VBUS 8 -600 -300 150 R 50 50 1 1 I
 X ~RST 9 -600 500 150 R 50 50 1 1 I
 X NC 10 400 -800 150 U 50 50 1 1 N N
 X GPIO.3 20 600 -100 150 L 50 50 1 1 B
-X SUSPEND 11 -600 200 150 R 50 50 1 1 I
+X SUSPEND 11 -600 200 150 R 50 50 1 1 O
 X GPIO.2 21 600 0 150 L 50 50 1 1 B
 X GPIO.7 12 600 -500 150 L 50 50 1 1 B
 X GPIO.1 22 600 100 150 L 50 50 1 1 B
@@ -110,9 +113,9 @@ X GPIO.0 23 600 200 150 L 50 50 1 1 B
 X GPIO.5 14 600 -300 150 L 50 50 1 1 B
 X SCL 24 600 400 150 L 50 50 1 1 O
 X GPIO.4 15 600 -200 150 L 50 50 1 1 B
-X GND 25 0 -800 150 U 50 50 1 1 I
+X GND 25 0 -800 150 U 50 50 1 1 W
 X VPP 16 -600 0 150 R 50 50 1 1 W
-X ~SUSPEND 17 -600 300 150 R 50 50 1 1 I
+X ~SUSPEND 17 -600 300 150 R 50 50 1 1 O
 X NC 18 200 -800 150 U 50 50 1 1 N N
 X NC 19 300 -800 150 U 50 50 1 1 N N
 ENDDRAW

From de53f05686b51f667086cabeffa3c9503044643e Mon Sep 17 00:00:00 2001
From: Andrew Bradford <andrew@bradfordembedded.com>
Date: Sun, 5 Mar 2017 13:46:37 -0500
Subject: [PATCH 6/9] silabs: Si4362: Fix KLC violations, add ground pad pin

Add pin 21 ground pad.

Prior to fixing, violations were:
checking component: Si4362
  Violating Rule 3.8
    Description and keywords properties contains information about the component.
  Violating EC01 - Extra Checking
    Check pins names against pin types.
  Violating EC03 - Extra Checking
    Check part reference, name and footprint position and alignment
  Violating EC04 - Extra Checking
    Check line width and background for box outlines parts.
  Violating EC05 - Extra Checking
    Pin numbers should not be duplicated, and all pins should be present
    Pin 4 is missing
    Pin 5 is missing
    Pin 7 is missing

Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
---
 library/silabs.dcm |  1 +
 library/silabs.lib | 20 ++++++++++++--------
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/library/silabs.dcm b/library/silabs.dcm
index f950adfe..89103396 100644
--- a/library/silabs.dcm
+++ b/library/silabs.dcm
@@ -20,6 +20,7 @@ $ENDCMP
 #
 $CMP Si4362
 D EZRadioPRO Low Current Receiver
+K radio receiver
 F http://www.silabs.com/Support%20Documents/TechnicalDocs/Si4362.pdf
 $ENDCMP
 #
diff --git a/library/silabs.lib b/library/silabs.lib
index 4c26c894..9f48adb3 100644
--- a/library/silabs.lib
+++ b/library/silabs.lib
@@ -124,29 +124,33 @@ ENDDEF
 # Si4362
 #
 DEF Si4362 U 0 40 Y Y 1 F N
-F0 "U" -400 700 50 H V C CNN
-F1 "Si4362" -300 -700 50 H V C CNN
-F2 "" 50 -1000 50 H I C CNN
+F0 "U" -200 775 50 H V R CNN
+F1 "Si4362" -200 700 50 H V R CNN
+F2 "Housings_DFN_QFN:QFN-20-1EP_4x4mm_Pitch0.5mm" 350 -700 50 H I L CNN
 F3 "" 50 -1000 50 H I C CNN
 $FPLIST
- QFN-20-1EP_4x4mm_Pitch0.5mm
+ QFN*4x4mm*Pitch0.5mm*
 $ENDFPLIST
 DRAW
-S -450 650 450 -650 0 1 0 f
+S -450 650 450 -650 0 1 10 f
 X SDN 1 -600 500 150 R 50 50 1 1 I
 X RXp 2 -600 400 150 R 50 50 1 1 I
 X RXn 3 -600 300 150 R 50 50 1 1 I
+X NC 4 100 -800 150 U 50 50 1 1 N N
+X NC 5 200 -800 150 U 50 50 1 1 N N
 X VDD 6 -100 800 150 D 50 50 1 1 W
+X NC 7 300 -800 150 U 50 50 1 1 N N
 X VDD 8 0 800 150 D 50 50 1 1 W
 X GPIO0 9 600 500 150 L 50 50 1 1 B
 X GPIO1 10 600 400 150 L 50 50 1 1 B
 X GPIO3 20 600 200 150 L 50 50 1 1 B
-X ~IRQ 11 600 -500 150 L 50 50 1 1 I
+X ~IRQ 11 600 -500 150 L 50 50 1 1 O
+X GND 21 -100 -800 150 U 50 50 1 1 W
 X SCLK 12 600 -400 150 L 50 50 1 1 I C
-X SDO 13 600 -300 150 L 50 50 1 1 I
+X SDO 13 600 -300 150 L 50 50 1 1 O
 X SDI 14 600 -200 150 L 50 50 1 1 I
 X ~SEL 15 600 -100 150 L 50 50 1 1 I
-X XOUT 16 -600 -200 150 R 50 50 1 1 I
+X XOUT 16 -600 -200 150 R 50 50 1 1 O
 X XIN 17 -600 -100 150 R 50 50 1 1 I
 X GND 18 0 -800 150 U 50 50 1 1 W
 X GPIO2 19 600 300 150 L 50 50 1 1 B

From 4efc6e0466d98a88dd4eacd9d12548640f298da2 Mon Sep 17 00:00:00 2001
From: Andrew Bradford <andrew@bradfordembedded.com>
Date: Sun, 5 Mar 2017 13:52:07 -0500
Subject: [PATCH 7/9] silabs: CP2102N-A01-CQFN24: fix KLC violations

Before fixing, violations were:
checking component: CP2102N-A01-GQFN24
  Violating EC03 - Extra Checking
    Check part reference, name and footprint position and alignment

Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
---
 library/silabs.lib | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/library/silabs.lib b/library/silabs.lib
index 9f48adb3..6c81162e 100644
--- a/library/silabs.lib
+++ b/library/silabs.lib
@@ -4,9 +4,9 @@ EESchema-LIBRARY Version 2.3
 # CP2102N-A01-GQFN24
 #
 DEF CP2102N-A01-GQFN24 U 0 40 Y Y 1 F N
-F0 "U" -400 800 50 H V C CNN
-F1 "CP2102N-A01-GQFN24" -550 -800 50 H V C CNN
-F2 "Housings_DFN_QFN:QFN-24-1EP_4x4mm_Pitch0.5mm" 50 -1050 50 H I C CNN
+F0 "U" -200 875 50 H V R CNN
+F1 "CP2102N-A01-GQFN24" -200 800 50 H V R CNN
+F2 "Housings_DFN_QFN:QFN-24-1EP_4x4mm_Pitch0.5mm" 450 -800 50 H I L CNN
 F3 "" 50 -1050 50 H I C CNN
 $FPLIST
  QFN*4x4mm*Pitch0.5mm*

From 82043d85b37b97b94701e1ecfa42776084fe3c9f Mon Sep 17 00:00:00 2001
From: Andrew Bradford <andrew@bradfordembedded.com>
Date: Sun, 5 Mar 2017 13:54:15 -0500
Subject: [PATCH 8/9] silabs: CP2104: Fix KLC violations

Before fixing, violations were:
checking component: CP2104
  Violating EC03 - Extra Checking
    Check part reference, name and footprint position and alignment

Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
---
 library/silabs.lib | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/library/silabs.lib b/library/silabs.lib
index 6c81162e..cf18bd69 100644
--- a/library/silabs.lib
+++ b/library/silabs.lib
@@ -44,9 +44,9 @@ ENDDEF
 # CP2104
 #
 DEF CP2104 U 0 40 Y Y 1 F N
-F0 "U" 300 1050 50 H V L CNN
-F1 "CP2104" 300 950 50 H V L CNN
-F2 "Housings_DFN_QFN:QFN-24-1EP_4x4mm_Pitch0.5mm" 300 850 50 H I L CNN
+F0 "U" -300 925 50 H V R CNN
+F1 "CP2104" -300 850 50 H V R CNN
+F2 "Housings_DFN_QFN:QFN-24-1EP_4x4mm_Pitch0.5mm" 150 -950 50 H I L CNN
 F3 "" -550 1250 50 H I C CNN
 $FPLIST
  QFN*4x4mm*Pitch0.5mm*

From 4f8ff6fe73ecd8744a6428c9c196d7f3be6754a9 Mon Sep 17 00:00:00 2001
From: Andrew Bradford <andrew@bradfordembedded.com>
Date: Sun, 5 Mar 2017 13:59:03 -0500
Subject: [PATCH 9/9] silabs: Si4735-D60-GU: Move NC pins, fix KLC violations

Move NC pins to not be at the same coordinates as GND pins.

Before fixing violations, they were:
checking component: Si4735-D60-GU
  Violating EC01 - Extra Checking
    Check pins names against pin types.

Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
---
 library/silabs.lib | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/library/silabs.lib b/library/silabs.lib
index cf18bd69..333fe064 100644
--- a/library/silabs.lib
+++ b/library/silabs.lib
@@ -162,7 +162,7 @@ ENDDEF
 DEF Si4735-D60-GU U 0 40 Y Y 1 F N
 F0 "U" -200 775 50 H V R CNN
 F1 "Si4735-D60-GU" -200 700 50 H V R CNN
-F2 "Housings_SSOP:SSOP-24_3.9x8.7mm_Pitch0.635mm" 150 -700 50 H I L CNN
+F2 "Housings_SSOP:SSOP-24_3.9x8.7mm_Pitch0.635mm" 250 -700 50 H I L CNN
 F3 "" 50 -1000 50 H I C CNN
 ALIAS Si4734-D60-GU Si4731-D60-GU Si4730-D60-GU
 $FPLIST
@@ -179,9 +179,9 @@ X NC 6 -600 -500 150 R 50 50 1 1 N N
 X NC 7 600 -500 150 L 50 50 1 1 N N
 X FMI 8 600 -300 150 L 50 50 1 1 I
 X RFGND 9 600 -400 150 L 50 50 1 1 W
-X NC 10 -100 -800 150 U 50 50 1 1 P N
+X NC 10 -200 -800 150 U 50 50 1 1 N N
 X VD 20 -100 800 150 D 50 50 1 1 W
-X NC 11 100 -800 150 U 50 50 1 1 P N
+X NC 11 200 -800 150 U 50 50 1 1 N N
 X VA 21 100 800 150 D 50 50 1 1 W
 X AMI 12 600 -200 150 L 50 50 1 1 I
 X DBYP 22 600 500 150 L 50 50 1 1 P