++
+This project template is the basis of a low speed expansion board (lure) for the
+Minnowboard MAX/Turbot.
+
This template includes a PCB edge defined according to the Minnowboard MAX or Turbot SBC
+with the low speed connector and mounting holes placed correctly to align the two boards.
+
+The board outline looks like the following:
+
+
+
Copyright (c) 2016 Michael Welling
+ + diff --git a/template/minnowboard-ls-lure/minnowboard-ls-lure-cache.lib b/template/minnowboard-ls-lure/minnowboard-ls-lure-cache.lib new file mode 100644 index 00000000..dcf010d6 --- /dev/null +++ b/template/minnowboard-ls-lure/minnowboard-ls-lure-cache.lib @@ -0,0 +1,118 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# +3V3 +# +DEF +3V3 #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "+3V3" 0 140 50 H V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +ALIAS +3.3V +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X +3V3 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# +5V +# +DEF +5V #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "+5V" 0 140 50 H V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X +5V 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# CONN_02X13 +# +DEF CONN_02X13 P 0 1 Y N 1 F N +F0 "P" 0 700 50 H V C CNN +F1 "CONN_02X13" 0 0 50 V V C CNN +F2 "" 0 -1150 50 H V C CNN +F3 "" 0 -1150 50 H V C CNN +$FPLIST + Pin_Header_Straight_2X13 + Pin_Header_Angled_2X13 + Socket_Strip_Straight_2X13 + Socket_Strip_Angled_2X13 +$ENDFPLIST +DRAW +S -100 -595 -50 -605 0 1 0 N +S -100 -495 -50 -505 0 1 0 N +S -100 -395 -50 -405 0 1 0 N +S -100 -295 -50 -305 0 1 0 N +S -100 -195 -50 -205 0 1 0 N +S -100 -95 -50 -105 0 1 0 N +S -100 5 -50 -5 0 1 0 N +S -100 105 -50 95 0 1 0 N +S -100 205 -50 195 0 1 0 N +S -100 305 -50 295 0 1 0 N +S -100 405 -50 395 0 1 0 N +S -100 505 -50 495 0 1 0 N +S -100 605 -50 595 0 1 0 N +S -100 650 100 -650 0 1 0 N +S 50 -595 100 -605 0 1 0 N +S 50 -495 100 -505 0 1 0 N +S 50 -395 100 -405 0 1 0 N +S 50 -295 100 -305 0 1 0 N +S 50 -195 100 -205 0 1 0 N +S 50 -95 100 -105 0 1 0 N +S 50 5 100 -5 0 1 0 N +S 50 105 100 95 0 1 0 N +S 50 205 100 195 0 1 0 N +S 50 305 100 295 0 1 0 N +S 50 405 100 395 0 1 0 N +S 50 505 100 495 0 1 0 N +S 50 605 100 595 0 1 0 N +X P1 1 -250 600 150 R 50 50 1 1 P +X P2 2 250 600 150 L 50 50 1 1 P +X P3 3 -250 500 150 R 50 50 1 1 P +X P4 4 250 500 150 L 50 50 1 1 P +X P5 5 -250 400 150 R 50 50 1 1 P +X P6 6 250 400 150 L 50 50 1 1 P +X P7 7 -250 300 150 R 50 50 1 1 P +X P8 8 250 300 150 L 50 50 1 1 P +X P9 9 -250 200 150 R 50 50 1 1 P +X P10 10 250 200 150 L 50 50 1 1 P +X P20 20 250 -300 150 L 50 50 1 1 P +X P11 11 -250 100 150 R 50 50 1 1 P +X P21 21 -250 -400 150 R 50 50 1 1 P +X P12 12 250 100 150 L 50 50 1 1 P +X P22 22 250 -400 150 L 50 50 1 1 P +X P13 13 -250 0 150 R 50 50 1 1 P +X P23 23 -250 -500 150 R 50 50 1 1 P +X P14 14 250 0 150 L 50 50 1 1 P +X P24 24 250 -500 150 L 50 50 1 1 P +X P15 15 -250 -100 150 R 50 50 1 1 P +X P25 25 -250 -600 150 R 50 50 1 1 P +X P16 16 250 -100 150 L 50 50 1 1 P +X P26 26 250 -600 150 L 50 50 1 1 P +X P17 17 -250 -200 150 R 50 50 1 1 P +X P18 18 250 -200 150 L 50 50 1 1 P +X P19 19 -250 -300 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/template/minnowboard-ls-lure/minnowboard-ls-lure.kicad_pcb b/template/minnowboard-ls-lure/minnowboard-ls-lure.kicad_pcb new file mode 100644 index 00000000..3da22f40 --- /dev/null +++ b/template/minnowboard-ls-lure/minnowboard-ls-lure.kicad_pcb @@ -0,0 +1,317 @@ +(kicad_pcb (version 4) (host pcbnew "(2015-08-07 BZR 6071, Git 6018bb6)-product") + + (general + (links 1) + (no_connects 1) + (area 96.444999 71.044999 195.502601 144.855001) + (thickness 1.6) + (drawings 5) + (tracks 0) + (zones 0) + (modules 5) + (nets 26) + ) + + (page A4) + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.25) + (trace_clearance 0.2) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.2) + (segment_width 0.2) + (edge_width 0.15) + (via_size 0.6) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.15) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 3.302 3.302) + (pad_drill 3.302) + (pad_to_mask_clearance 0.0762) + (aux_axis_origin 96.52 144.78) + (grid_origin 96.52 144.78) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x000fc_80000001) + (usegerberextensions false) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15) + (hpglpenoverlay 2) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 0) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 GND) + (net 2 +5V) + (net 3 +3V3) + (net 4 GPIO_SPI_CS#) + (net 5 GPIO_UART1_TXD) + (net 6 GPIO_SPI_MISO) + (net 7 GPIO_UART1_RXD) + (net 8 GPIO_SPI_MOSI) + (net 9 GPIO_UART1_CTS) + (net 10 GPIO_SPI_CLK) + (net 11 GPIO_UART1_RTS) + (net 12 GPIO_I2C_SCL) + (net 13 GPIO_I2S_CLK) + (net 14 GPIO_I2C_SDA) + (net 15 GPIO_I2S_FRM) + (net 16 GPIO_UART2_TXD) + (net 17 GPIO_I2S_DO) + (net 18 GPIO_UART2_RXD) + (net 19 GPIO_I2S_DI) + (net 20 GPIO_S5_0) + (net 21 GPIO_PWM0) + (net 22 GPIO_S5_1) + (net 23 GPIO_PWM1) + (net 24 GPIO_S5_2) + (net 25 I2SMCLK_GPIO) + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.6) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net +3V3) + (add_net +5V) + (add_net GND) + (add_net GPIO_I2C_SCL) + (add_net GPIO_I2C_SDA) + (add_net GPIO_I2S_CLK) + (add_net GPIO_I2S_DI) + (add_net GPIO_I2S_DO) + (add_net GPIO_I2S_FRM) + (add_net GPIO_PWM0) + (add_net GPIO_PWM1) + (add_net GPIO_S5_0) + (add_net GPIO_S5_1) + (add_net GPIO_S5_2) + (add_net GPIO_SPI_CLK) + (add_net GPIO_SPI_CS#) + (add_net GPIO_SPI_MISO) + (add_net GPIO_SPI_MOSI) + (add_net GPIO_UART1_CTS) + (add_net GPIO_UART1_RTS) + (add_net GPIO_UART1_RXD) + (add_net GPIO_UART1_TXD) + (add_net GPIO_UART2_RXD) + (add_net GPIO_UART2_TXD) + (add_net I2SMCLK_GPIO) + ) + + (module Pin_Headers:Pin_Header_Straight_2x13 (layer F.Cu) (tedit 576C9AA0) (tstamp 57710C62) + (at 109.855 142.24 90) + (descr "Through hole pin header") + (tags "pin header") + (path /576C994F) + (fp_text reference P1 (at 1.27 -3.175 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value CONN_02X13 (at 5.08 3.175 180) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.75 -1.75) (end -1.75 32.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.3 -1.75) (end 4.3 32.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 -1.75) (end 4.3 -1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 32.25) (end 4.3 32.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.81 -1.27) (end 3.81 31.75) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.27 1.27) (end -1.27 31.75) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.81 31.75) (end -1.27 31.75) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.81 -1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 0 -1.55) (end -1.55 -1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 -1.55) (end -1.55 0) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 1 GND)) + (pad 2 thru_hole oval (at 2.54 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 1 GND)) + (pad 3 thru_hole oval (at 0 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 2 +5V)) + (pad 4 thru_hole oval (at 2.54 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 3 +3V3)) + (pad 5 thru_hole oval (at 0 5.08 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 4 GPIO_SPI_CS#)) + (pad 6 thru_hole oval (at 2.54 5.08 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 5 GPIO_UART1_TXD)) + (pad 7 thru_hole oval (at 0 7.62 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 6 GPIO_SPI_MISO)) + (pad 8 thru_hole oval (at 2.54 7.62 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 7 GPIO_UART1_RXD)) + (pad 9 thru_hole oval (at 0 10.16 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 8 GPIO_SPI_MOSI)) + (pad 10 thru_hole oval (at 2.54 10.16 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 9 GPIO_UART1_CTS)) + (pad 11 thru_hole oval (at 0 12.7 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 10 GPIO_SPI_CLK)) + (pad 12 thru_hole oval (at 2.54 12.7 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 11 GPIO_UART1_RTS)) + (pad 13 thru_hole oval (at 0 15.24 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 12 GPIO_I2C_SCL)) + (pad 14 thru_hole oval (at 2.54 15.24 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 13 GPIO_I2S_CLK)) + (pad 15 thru_hole oval (at 0 17.78 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 14 GPIO_I2C_SDA)) + (pad 16 thru_hole oval (at 2.54 17.78 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 15 GPIO_I2S_FRM)) + (pad 17 thru_hole oval (at 0 20.32 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 16 GPIO_UART2_TXD)) + (pad 18 thru_hole oval (at 2.54 20.32 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 17 GPIO_I2S_DO)) + (pad 19 thru_hole oval (at 0 22.86 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 18 GPIO_UART2_RXD)) + (pad 20 thru_hole oval (at 2.54 22.86 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 19 GPIO_I2S_DI)) + (pad 21 thru_hole oval (at 0 25.4 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 20 GPIO_S5_0)) + (pad 22 thru_hole oval (at 2.54 25.4 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 21 GPIO_PWM0)) + (pad 23 thru_hole oval (at 0 27.94 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 22 GPIO_S5_1)) + (pad 24 thru_hole oval (at 2.54 27.94 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 23 GPIO_PWM1)) + (pad 25 thru_hole oval (at 0 30.48 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 24 GPIO_S5_2)) + (pad 26 thru_hole oval (at 2.54 30.48 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 25 I2SMCLK_GPIO)) + (model Pin_Headers.3dshapes/Pin_Header_Straight_2x13.wrl + (at (xyz 0.05 -0.6 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 90)) + ) + ) + + (module minnowboard-ls-lure:Mount (layer F.Cu) (tedit 576DC0A6) (tstamp 576DB8B1) + (at 100.33 140.97) + (descr "module 1 pin (ou trou mecanique de percage)") + (tags DEV) + (fp_text reference REF** (at 0 -3.048) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Mount (at 0 2.794) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad "" np_thru_hole circle (at 0 0) (size 6.604 6.604) (drill 3.302) (layers *.Cu *.Mask F.SilkS)) + ) + + (module minnowboard-ls-lure:Mount (layer F.Cu) (tedit 576DC0A6) (tstamp 576DB8A5) + (at 100.33 74.93) + (descr "module 1 pin (ou trou mecanique de percage)") + (tags DEV) + (fp_text reference REF** (at 0 -3.048) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Mount (at 0 2.794) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad "" np_thru_hole circle (at 0 0) (size 6.604 6.604) (drill 3.302) (layers *.Cu *.Mask F.SilkS)) + ) + + (module minnowboard-ls-lure:Mount (layer F.Cu) (tedit 576DC0A6) (tstamp 576DB8BC) + (at 191.77 74.93) + (descr "module 1 pin (ou trou mecanique de percage)") + (tags DEV) + (fp_text reference REF** (at 0 -3.048) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Mount (at 0 2.794) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad "" np_thru_hole circle (at 0 0) (size 6.604 6.604) (drill 3.302) (layers *.Cu *.Mask F.SilkS)) + ) + + (module minnowboard-ls-lure:Mount (layer F.Cu) (tedit 576DC0A6) (tstamp 576DB8C7) + (at 191.77 140.97) + (descr "module 1 pin (ou trou mecanique de percage)") + (tags DEV) + (fp_text reference REF** (at 0 -3.048) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Mount (at 0 2.794) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad "" np_thru_hole circle (at 0 0) (size 6.604 6.604) (drill 3.302) (layers *.Cu *.Mask F.SilkS)) + ) + + (target plus (at 96.52 144.78) (size 5) (width 0.15) (layer Edge.Cuts)) + (gr_line (start 96.52 71.12) (end 96.52 144.78) (angle 90) (layer Edge.Cuts) (width 0.15)) + (gr_line (start 195.4276 71.12) (end 96.52 71.12) (angle 90) (layer Edge.Cuts) (width 0.15)) + (gr_line (start 195.4276 144.78) (end 195.4276 71.12) (angle 90) (layer Edge.Cuts) (width 0.15)) + (gr_line (start 96.52 144.78) (end 195.4276 144.78) (angle 90) (layer Edge.Cuts) (width 0.15)) + + (zone (net 0) (net_name "") (layer B.Cu) (tstamp 57710D56) (hatch edge 0.508) + (connect_pads (clearance 0.508)) + (min_thickness 0.254) + (keepout (tracks not_allowed) (vias not_allowed) (copperpour allowed)) + (fill (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508)) + (polygon + (pts + (xy 115.57 109.855) (xy 96.52 109.855) (xy 96.52 90.805) (xy 115.57 90.805) (xy 115.57 109.855) + ) + ) + ) + (zone (net 0) (net_name "") (layer B.Cu) (tstamp 57710D74) (hatch edge 0.508) + (connect_pads (clearance 0.508)) + (min_thickness 0.254) + (keepout (tracks not_allowed) (vias not_allowed) (copperpour allowed)) + (fill (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508)) + (polygon + (pts + (xy 195.58 109.855) (xy 176.53 109.855) (xy 176.53 90.805) (xy 195.58 90.805) + ) + ) + ) +) diff --git a/template/minnowboard-ls-lure/minnowboard-ls-lure.net b/template/minnowboard-ls-lure/minnowboard-ls-lure.net new file mode 100644 index 00000000..ea99506b --- /dev/null +++ b/template/minnowboard-ls-lure/minnowboard-ls-lure.net @@ -0,0 +1,116 @@ +(export (version D) + (design + (source /home/michael/projects/kicad/pcbs/minnowboard-ls-lure/minnowboard-ls-lure.sch) + (date "Fri 24 Jun 2016 06:50:03 PM CDT") + (tool "Eeschema (2015-08-07 BZR 6071, Git 6018bb6)-product") + (sheet (number 1) (name /) (tstamps /) + (title_block + (title) + (company) + (rev) + (date) + (source minnowboard-ls-lure.sch) + (comment (number 1) (value "")) + (comment (number 2) (value "")) + (comment (number 3) (value "")) + (comment (number 4) (value ""))))) + (components + (comp (ref P1) + (value CONN_02X13) + (footprint Pin_Headers:Pin_Header_Straight_2x13) + (libsource (lib conn) (part CONN_02X13)) + (sheetpath (names /) (tstamps /)) + (tstamp 576C994F))) + (libparts + (libpart (lib conn) (part CONN_02X13) + (description "Connector, double row, 02x13") + (footprints + (fp Pin_Header_Straight_2X13) + (fp Pin_Header_Angled_2X13) + (fp Socket_Strip_Straight_2X13) + (fp Socket_Strip_Angled_2X13)) + (fields + (field (name Reference) P) + (field (name Value) CONN_02X13)) + (pins + (pin (num 1) (name P1) (type passive)) + (pin (num 2) (name P2) (type passive)) + (pin (num 3) (name P3) (type passive)) + (pin (num 4) (name P4) (type passive)) + (pin (num 5) (name P5) (type passive)) + (pin (num 6) (name P6) (type passive)) + (pin (num 7) (name P7) (type passive)) + (pin (num 8) (name P8) (type passive)) + (pin (num 9) (name P9) (type passive)) + (pin (num 10) (name P10) (type passive)) + (pin (num 11) (name P11) (type passive)) + (pin (num 12) (name P12) (type passive)) + (pin (num 13) (name P13) (type passive)) + (pin (num 14) (name P14) (type passive)) + (pin (num 15) (name P15) (type passive)) + (pin (num 16) (name P16) (type passive)) + (pin (num 17) (name P17) (type passive)) + (pin (num 18) (name P18) (type passive)) + (pin (num 19) (name P19) (type passive)) + (pin (num 20) (name P20) (type passive)) + (pin (num 21) (name P21) (type passive)) + (pin (num 22) (name P22) (type passive)) + (pin (num 23) (name P23) (type passive)) + (pin (num 24) (name P24) (type passive)) + (pin (num 25) (name P25) (type passive)) + (pin (num 26) (name P26) (type passive))))) + (libraries + (library (logical conn) + (uri /home/michael/projects/kicad/kicad-library/library/conn.lib))) + (nets + (net (code 1) (name GPIO_PWM1) + (node (ref P1) (pin 24))) + (net (code 2) (name GPIO_S5_0) + (node (ref P1) (pin 21))) + (net (code 3) (name GPIO_UART2_RXD) + (node (ref P1) (pin 19))) + (net (code 4) (name GPIO_UART2_TXD) + (node (ref P1) (pin 17))) + (net (code 5) (name GPIO_I2C_SDA) + (node (ref P1) (pin 15))) + (net (code 6) (name GPIO_I2C_SCL) + (node (ref P1) (pin 13))) + (net (code 7) (name GPIO_SPI_CLK) + (node (ref P1) (pin 11))) + (net (code 8) (name GPIO_SPI_MOSI) + (node (ref P1) (pin 9))) + (net (code 9) (name GPIO_SPI_MISO) + (node (ref P1) (pin 7))) + (net (code 10) (name GPIO_SPI_CS#) + (node (ref P1) (pin 5))) + (net (code 11) (name I2SMCLK_GPIO) + (node (ref P1) (pin 26))) + (net (code 12) (name GPIO_S5_1) + (node (ref P1) (pin 23))) + (net (code 13) (name GPIO_PWM0) + (node (ref P1) (pin 22))) + (net (code 14) (name GPIO_I2S_DI) + (node (ref P1) (pin 20))) + (net (code 15) (name GPIO_I2S_DO) + (node (ref P1) (pin 18))) + (net (code 16) (name GPIO_I2S_FRM) + (node (ref P1) (pin 16))) + (net (code 17) (name GPIO_I2S_CLK) + (node (ref P1) (pin 14))) + (net (code 18) (name GPIO_UART1_RTS) + (node (ref P1) (pin 12))) + (net (code 19) (name GPIO_UART1_CTS) + (node (ref P1) (pin 10))) + (net (code 20) (name GPIO_UART1_RXD) + (node (ref P1) (pin 8))) + (net (code 21) (name GPIO_UART1_TXD) + (node (ref P1) (pin 6))) + (net (code 22) (name GPIO_S5_2) + (node (ref P1) (pin 25))) + (net (code 23) (name +5V) + (node (ref P1) (pin 3))) + (net (code 24) (name GND) + (node (ref P1) (pin 1)) + (node (ref P1) (pin 2))) + (net (code 25) (name +3V3) + (node (ref P1) (pin 4))))) \ No newline at end of file diff --git a/template/minnowboard-ls-lure/minnowboard-ls-lure.pretty/Mount.kicad_mod b/template/minnowboard-ls-lure/minnowboard-ls-lure.pretty/Mount.kicad_mod new file mode 100644 index 00000000..e25456e5 --- /dev/null +++ b/template/minnowboard-ls-lure/minnowboard-ls-lure.pretty/Mount.kicad_mod @@ -0,0 +1,11 @@ +(module Mount (layer F.Cu) (tedit 576DC0A6) + (descr "module 1 pin (ou trou mecanique de percage)") + (tags DEV) + (fp_text reference REF** (at 0 -3.048) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Mount (at 0 2.794) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad "" np_thru_hole circle (at 0 0) (size 6.604 6.604) (drill 3.302) (layers *.Cu *.Mask F.SilkS)) +) diff --git a/template/minnowboard-ls-lure/minnowboard-ls-lure.pro b/template/minnowboard-ls-lure/minnowboard-ls-lure.pro new file mode 100644 index 00000000..b1b6a53d --- /dev/null +++ b/template/minnowboard-ls-lure/minnowboard-ls-lure.pro @@ -0,0 +1,60 @@ +update=Thu 23 Jun 2016 08:17:46 PM CDT +version=1 +last_client=kicad +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[general] +version=1 +[eeschema] +version=1 +LibDir=/home/michael/projects/kicad/kicad-library/library +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=microcontrollers +LibName13=dsp +LibName14=microchip +LibName15=analog_switches +LibName16=motorola +LibName17=texas +LibName18=intel +LibName19=audio +LibName20=interface +LibName21=digital-audio +LibName22=philips +LibName23=display +LibName24=cypress +LibName25=siliconi +LibName26=opto +LibName27=atmel +LibName28=contrib +LibName29=valves diff --git a/template/minnowboard-ls-lure/minnowboard-ls-lure.sch b/template/minnowboard-ls-lure/minnowboard-ls-lure.sch new file mode 100644 index 00000000..411d6b30 --- /dev/null +++ b/template/minnowboard-ls-lure/minnowboard-ls-lure.sch @@ -0,0 +1,205 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:minnowboard-ls-lure-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L CONN_02X13 P1 +U 1 1 576C994F +P 2600 2350 +F 0 "P1" H 2600 3050 50 0000 C CNN +F 1 "CONN_02X13" V 2600 2350 50 0000 C CNN +F 2 "Pin_Headers:Pin_Header_Straight_2x13" H 2600 1200 50 0001 C CNN +F 3 "" H 2600 1200 50 0000 C CNN + 1 2600 2350 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR? +U 1 1 576DC243 +P 2950 3000 +F 0 "#PWR?" H 2950 2750 50 0001 C CNN +F 1 "GND" H 2950 2850 50 0000 C CNN +F 2 "" H 2950 3000 50 0000 C CNN +F 3 "" H 2950 3000 50 0000 C CNN + 1 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR? +U 1 1 576DC271 +P 2250 3000 +F 0 "#PWR?" H 2250 2750 50 0001 C CNN +F 1 "GND" H 2250 2850 50 0000 C CNN +F 2 "" H 2250 3000 50 0000 C CNN +F 3 "" H 2250 3000 50 0000 C CNN + 1 2250 3000 + 1 0 0 -1 +$EndComp +$Comp +L +3.3V #PWR? +U 1 1 576DC2D3 +P 3050 1650 +F 0 "#PWR?" H 3050 1500 50 0001 C CNN +F 1 "+3.3V" H 3050 1790 50 0000 C CNN +F 2 "" H 3050 1650 50 0000 C CNN +F 3 "" H 3050 1650 50 0000 C CNN + 1 3050 1650 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR? +U 1 1 576DC2E9 +P 2150 1650 +F 0 "#PWR?" H 2150 1500 50 0001 C CNN +F 1 "+5V" H 2150 1790 50 0000 C CNN +F 2 "" H 2150 1650 50 0000 C CNN +F 3 "" H 2150 1650 50 0000 C CNN + 1 2150 1650 + 1 0 0 -1 +$EndComp +Text GLabel 2100 1950 0 45 BiDi ~ 0 +GPIO_SPI_CS# +Text GLabel 2100 2050 0 45 BiDi ~ 0 +GPIO_SPI_MISO +Text GLabel 2100 2150 0 45 BiDi ~ 0 +GPIO_SPI_MOSI +Text GLabel 2100 2250 0 45 BiDi ~ 0 +GPIO_SPI_CLK +Text GLabel 2100 2350 0 45 BiDi ~ 0 +GPIO_I2C_SCL +Text GLabel 2100 2450 0 45 BiDi ~ 0 +GPIO_I2C_SDA +Text GLabel 2100 2550 0 45 BiDi ~ 0 +GPIO_UART2_TXD +Text GLabel 2100 2650 0 45 BiDi ~ 0 +GPIO_UART2_RXD +Text GLabel 2100 2750 0 45 BiDi ~ 0 +GPIO_S5_0 +Text GLabel 2100 2850 0 45 BiDi ~ 0 +GPIO_S5_1 +Text GLabel 2100 2950 0 45 BiDi ~ 0 +GPIO_S5_2 +Text GLabel 3075 1950 2 45 BiDi ~ 0 +GPIO_UART1_TXD +Text GLabel 3075 2050 2 45 Input ~ 0 +GPIO_UART1_RXD +Text GLabel 3075 2150 2 45 BiDi ~ 0 +GPIO_UART1_CTS +Text GLabel 3075 2250 2 45 BiDi ~ 0 +GPIO_UART1_RTS +Text GLabel 3075 2350 2 45 BiDi ~ 0 +GPIO_I2S_CLK +Text GLabel 3075 2450 2 45 BiDi ~ 0 +GPIO_I2S_FRM +Text GLabel 3075 2550 2 45 BiDi ~ 0 +GPIO_I2S_DO +Text GLabel 3075 2650 2 45 BiDi ~ 0 +GPIO_I2S_DI +Text GLabel 3075 2750 2 45 BiDi ~ 0 +GPIO_PWM0 +Text GLabel 3075 2850 2 45 BiDi ~ 0 +GPIO_PWM1 +Text GLabel 3075 2950 2 45 BiDi ~ 0 +I2SMCLK_GPIO +Wire Wire Line + 2100 1950 2350 1950 +Wire Wire Line + 2100 2050 2350 2050 +Wire Wire Line + 2100 2150 2350 2150 +Wire Wire Line + 2100 2250 2350 2250 +Wire Wire Line + 2100 2350 2350 2350 +Wire Wire Line + 2100 2450 2350 2450 +Wire Wire Line + 2100 2550 2350 2550 +Wire Wire Line + 2100 2650 2350 2650 +Wire Wire Line + 2100 2750 2350 2750 +Wire Wire Line + 2100 2850 2350 2850 +Wire Wire Line + 2100 2950 2350 2950 +Wire Wire Line + 2850 1950 3075 1950 +Wire Wire Line + 2850 2050 3075 2050 +Wire Wire Line + 2850 2150 3075 2150 +Wire Wire Line + 2850 2250 3075 2250 +Wire Wire Line + 2850 2350 3075 2350 +Wire Wire Line + 2850 2450 3075 2450 +Wire Wire Line + 2850 2550 3075 2550 +Wire Wire Line + 2850 2650 3075 2650 +Wire Wire Line + 2850 2750 3075 2750 +Wire Wire Line + 2850 2850 3075 2850 +Wire Wire Line + 2850 2950 3075 2950 +Wire Wire Line + 2850 1750 2950 1750 +Wire Wire Line + 2950 1750 2950 3000 +Wire Wire Line + 3050 1850 3050 1650 +Wire Wire Line + 2850 1850 3050 1850 +Wire Wire Line + 2350 1750 2250 1750 +Wire Wire Line + 2250 1750 2250 3000 +Wire Wire Line + 2150 1650 2150 1850 +Wire Wire Line + 2150 1850 2350 1850 +$EndSCHEMATC