Add Xilinx 7 series devices
This commit is contained in:
parent
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EESchema-DOCLIB Version 2.0 Date: Fri 27 Mar 2015 15:45:50 PM PDT
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#
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$CMP XC7A15T-CPG236
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K FPGA
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D Artix 7 T 15 XC7A15T-CPG236
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$ENDCMP
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#
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$CMP XC7A15T-CSG324
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K FPGA
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D Artix 7 T 15 XC7A15T-CSG324
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$ENDCMP
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#
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$CMP XC7A15T-CSG325
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K FPGA
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D Artix 7 T 15 XC7A15T-CSG325
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$ENDCMP
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#
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$CMP XC7A15T-FGG484
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K FPGA
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D Artix 7 T 15 XC7A15T-FGG484
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$ENDCMP
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#
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$CMP XC7A15T-FTG256
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K FPGA
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D Artix 7 T 15 XC7A15T-FTG256
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$ENDCMP
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#
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$CMP XC7A35T-CPG236
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K FPGA
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D Artix 7 T 35 XC7A35T-CPG236
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$ENDCMP
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#
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$CMP XC7A35T-CSG324
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K FPGA
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D Artix 7 T 35 XC7A35T-CSG324
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$ENDCMP
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#
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$CMP XC7A35T-CSG325
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K FPGA
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D Artix 7 T 35 XC7A35T-CSG325
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$ENDCMP
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#
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$CMP XC7A35T-FGG484
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K FPGA
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D Artix 7 T 35 XC7A35T-FGG484
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$ENDCMP
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#
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$CMP XC7A35T-FTG256
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K FPGA
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D Artix 7 T 35 XC7A35T-FTG256
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$ENDCMP
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#
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$CMP XC7A50T-CPG236
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K FPGA
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D Artix 7 T 50 XC7A50T-CPG236
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$ENDCMP
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#
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$CMP XC7A50T-CSG324
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K FPGA
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D Artix 7 T 50 XC7A50T-CSG324
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$ENDCMP
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#
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$CMP XC7A50T-CSG325
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K FPGA
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D Artix 7 T 50 XC7A50T-CSG325
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$ENDCMP
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#
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$CMP XC7A50T-FGG484
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K FPGA
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D Artix 7 T 50 XC7A50T-FGG484
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$ENDCMP
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#
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$CMP XC7A50T-FTG256
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K FPGA
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D Artix 7 T 50 XC7A50T-FTG256
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$ENDCMP
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#
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$CMP XC7A75T-CSG324
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K FPGA
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D Artix 7 T 75 XC7A75T-CSG324
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$ENDCMP
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#
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$CMP XC7A75T-FGG484
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K FPGA
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D Artix 7 T 75 XC7A75T-FGG484
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$ENDCMP
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#
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$CMP XC7A75T-FGG676
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K FPGA
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D Artix 7 T 75 XC7A75T-FGG676
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$ENDCMP
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#
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$CMP XC7A75T-FTG256
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K FPGA
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D Artix 7 T 75 XC7A75T-FTG256
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$ENDCMP
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#
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$CMP XC7A100T-CSG324
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K FPGA
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D Artix 7 T 100 XC7A100T-CSG324
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$ENDCMP
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#
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$CMP XC7A100T-FGG484
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K FPGA
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D Artix 7 T 100 XC7A100T-FGG484
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$ENDCMP
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#
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$CMP XC7A100T-FGG676
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K FPGA
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D Artix 7 T 100 XC7A100T-FGG676
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$ENDCMP
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#
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$CMP XC7A100T-FTG256
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K FPGA
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D Artix 7 T 100 XC7A100T-FTG256
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$ENDCMP
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#
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$CMP XC7A200T-FBG484
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K FPGA
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D Artix 7 T 200 XC7A200T-FBG484
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$ENDCMP
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#
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$CMP XC7A200T-FBG676
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K FPGA
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D Artix 7 T 200 XC7A200T-FBG676
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$ENDCMP
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#
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$CMP XC7A200T-FFG1156
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K FPGA
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D Artix 7 T 200 XC7A200T-FFG1156
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$ENDCMP
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#
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$CMP XC7A200T-SBG484
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K FPGA
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D Artix 7 T 200 XC7A200T-SBG484
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$ENDCMP
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#
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#End Doc Library
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EESchema-DOCLIB Version 2.0 Date: Fri 27 Mar 2015 15:45:45 PM PDT
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#
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$CMP XC7K70T-FBG484
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K FPGA
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D Kintex 7 T 70 XC7K70T-FBG484
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$ENDCMP
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#
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$CMP XC7K70T-FBG676
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K FPGA
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D Kintex 7 T 70 XC7K70T-FBG676
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$ENDCMP
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#
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$CMP XC7K160T-FBG484
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K FPGA
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D Kintex 7 T 160 XC7K160T-FBG484
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$ENDCMP
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#
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$CMP XC7K160T-FBG676
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K FPGA
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D Kintex 7 T 160 XC7K160T-FBG676
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$ENDCMP
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#
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$CMP XC7K160T-FFG676
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K FPGA
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D Kintex 7 T 160 XC7K160T-FFG676
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$ENDCMP
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#
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$CMP XC7K325T-FBG676
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K FPGA
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D Kintex 7 T 325 XC7K325T-FBG676
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$ENDCMP
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#
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$CMP XC7K325T-FBG900
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K FPGA
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D Kintex 7 T 325 XC7K325T-FBG900
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$ENDCMP
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#
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$CMP XC7K325T-FFG676
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K FPGA
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D Kintex 7 T 325 XC7K325T-FFG676
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$ENDCMP
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#
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$CMP XC7K325T-FFG900
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K FPGA
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D Kintex 7 T 325 XC7K325T-FFG900
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$ENDCMP
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#
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$CMP XC7K355T-FFG901
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K FPGA
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D Kintex 7 T 355 XC7K355T-FFG901
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$ENDCMP
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#
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$CMP XC7K410T-FBG676
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K FPGA
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D Kintex 7 T 410 XC7K410T-FBG676
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$ENDCMP
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#
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$CMP XC7K410T-FBG900
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K FPGA
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D Kintex 7 T 410 XC7K410T-FBG900
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$ENDCMP
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#
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$CMP XC7K410T-FFG676
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K FPGA
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D Kintex 7 T 410 XC7K410T-FFG676
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$ENDCMP
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#
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$CMP XC7K410T-FFG900
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K FPGA
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D Kintex 7 T 410 XC7K410T-FFG900
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$ENDCMP
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#
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$CMP XC7K420T-FFG901
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K FPGA
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D Kintex 7 T 420 XC7K420T-FFG901
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$ENDCMP
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#
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$CMP XC7K420T-FFG1156
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K FPGA
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D Kintex 7 T 420 XC7K420T-FFG1156
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$ENDCMP
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#
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$CMP XC7K480T-FFG901
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K FPGA
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D Kintex 7 T 480 XC7K480T-FFG901
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$ENDCMP
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#
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$CMP XC7K480T-FFG1156
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K FPGA
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D Kintex 7 T 480 XC7K480T-FFG1156
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$ENDCMP
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#
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#End Doc Library
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EESchema-DOCLIB Version 2.0 Date: Fri 27 Mar 2015 15:45:39 PM PDT
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#
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$CMP XC7V585T-FFG1157
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K FPGA
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D Virtex 7 T 585 XC7V585T-FFG1157
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$ENDCMP
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#
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$CMP XC7V585T-FFG1761
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K FPGA
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D Virtex 7 T 585 XC7V585T-FFG1761
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$ENDCMP
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#
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$CMP XC7V2000T-FHG1761
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K FPGA
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D Virtex 7 T 2000 XC7V2000T-FHG1761
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$ENDCMP
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#
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$CMP XC7V2000T-FLG1925
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K FPGA
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D Virtex 7 T 2000 XC7V2000T-FLG1925
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$ENDCMP
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#
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$CMP XC7VH580T-FLG1155
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K FPGA
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D Virtex 7 HT 580 XC7VH580T-FLG1155
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$ENDCMP
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#
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$CMP XC7VH580T-FLG1931
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K FPGA
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D Virtex 7 HT 580 XC7VH580T-FLG1931
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$ENDCMP
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#
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$CMP XC7VH870T-FLG1932
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K FPGA
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D Virtex 7 HT 870 XC7VH870T-FLG1932
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$ENDCMP
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#
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$CMP XC7VX330T-FFG1157
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K FPGA
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D Virtex 7 XT 330 XC7VX330T-FFG1157
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$ENDCMP
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#
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$CMP XC7VX330T-FFG1761
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K FPGA
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D Virtex 7 XT 330 XC7VX330T-FFG1761
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$ENDCMP
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#
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$CMP XC7VX415T-FFG1157
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K FPGA
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D Virtex 7 XT 415 XC7VX415T-FFG1157
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$ENDCMP
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#
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$CMP XC7VX415T-FFG1158
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K FPGA
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D Virtex 7 XT 415 XC7VX415T-FFG1158
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$ENDCMP
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#
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$CMP XC7VX415T-FFG1927
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K FPGA
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D Virtex 7 XT 415 XC7VX415T-FFG1927
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$ENDCMP
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#
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$CMP XC7VX485T-FFG1157
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K FPGA
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D Virtex 7 XT 485 XC7VX485T-FFG1157
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$ENDCMP
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#
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$CMP XC7VX485T-FFG1158
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K FPGA
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D Virtex 7 XT 485 XC7VX485T-FFG1158
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$ENDCMP
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#
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$CMP XC7VX485T-FFG1761
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K FPGA
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D Virtex 7 XT 485 XC7VX485T-FFG1761
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$ENDCMP
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#
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$CMP XC7VX485T-FFG1927
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K FPGA
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D Virtex 7 XT 485 XC7VX485T-FFG1927
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$ENDCMP
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#
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$CMP XC7VX485T-FFG1930
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K FPGA
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D Virtex 7 XT 485 XC7VX485T-FFG1930
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$ENDCMP
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#
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$CMP XC7VX550T-FFG1158
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K FPGA
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D Virtex 7 XT 550 XC7VX550T-FFG1158
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$ENDCMP
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#
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$CMP XC7VX550T-FFG1927
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K FPGA
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D Virtex 7 XT 550 XC7VX550T-FFG1927
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$ENDCMP
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#
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$CMP XC7VX690T-FFG1157
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K FPGA
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D Virtex 7 XT 690 XC7VX690T-FFG1157
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$ENDCMP
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#
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$CMP XC7VX690T-FFG1158
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K FPGA
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D Virtex 7 XT 690 XC7VX690T-FFG1158
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$ENDCMP
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#
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$CMP XC7VX690T-FFG1761
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K FPGA
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D Virtex 7 XT 690 XC7VX690T-FFG1761
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$ENDCMP
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#
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$CMP XC7VX690T-FFG1926
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K FPGA
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D Virtex 7 XT 690 XC7VX690T-FFG1926
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$ENDCMP
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#
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$CMP XC7VX690T-FFG1927
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K FPGA
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D Virtex 7 XT 690 XC7VX690T-FFG1927
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$ENDCMP
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#
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$CMP XC7VX690T-FFG1930
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K FPGA
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D Virtex 7 XT 690 XC7VX690T-FFG1930
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$ENDCMP
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#
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$CMP XC7VX980T-FFG1926
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K FPGA
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D Virtex 7 XT 980 XC7VX980T-FFG1926
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$ENDCMP
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#
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$CMP XC7VX980T-FFG1928
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K FPGA
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D Virtex 7 XT 980 XC7VX980T-FFG1928
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$ENDCMP
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#
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$CMP XC7VX980T-FFG1930
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K FPGA
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D Virtex 7 XT 980 XC7VX980T-FFG1930
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$ENDCMP
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#
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$CMP XC7VX1140T-FLG1926
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K FPGA
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D Virtex 7 XT 1140 XC7VX1140T-FLG1926
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$ENDCMP
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#
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$CMP XC7VX1140T-FLG1928
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K FPGA
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D Virtex 7 XT 1140 XC7VX1140T-FLG1928
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$ENDCMP
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#
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$CMP XC7VX1140T-FLG1930
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K FPGA
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D Virtex 7 XT 1140 XC7VX1140T-FLG1930
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$ENDCMP
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#
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#End Doc Library
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File diff suppressed because it is too large
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