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Add simple internal schematics

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evanshultz 2017-11-23 08:51:28 -08:00 committed by GitHub
parent 2f38994b65
commit 7fd6118641
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 133 additions and 31 deletions
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164
library/analog_devices.lib
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@ -121,6 +121,21 @@ $FPLIST
LQFP*7x7mm*Pitch0.5mm*
$ENDFPLIST
DRAW
T 0 350 50 60 0 0 0 10-BIT Normal 0 C C
T 0 350 -50 60 0 0 0 DAC Normal 0 C C
T 0 500 900 60 0 0 0 ON-BOARD Normal 0 C C
T 900 -450 0 60 0 0 0 PARALLEL~DATA~INTERFACE Normal 0 C C
T 0 500 800 60 0 0 0 REFERENCE Normal 0 C C
T 0 -100 -50 60 0 0 0 ROM Normal 0 C C
T 0 -100 50 60 0 0 0 SIN Normal 0 C C
S -250 150 50 -150 0 0 0 N
P 2 0 0 0 -250 0 -350 0 N
P 2 0 0 0 150 0 50 0 N
P 3 0 0 0 300 150 300 500 550 500 N
P 3 0 0 0 350 -500 300 -500 300 -150 N
P 4 0 0 0 -800 850 -350 850 -350 -750 -800 -750 N
P 4 0 0 0 800 650 200 650 200 1000 800 1000 N
P 6 0 0 0 600 0 450 150 150 150 150 -150 450 -150 600 0 N
S -800 1500 800 -1500 0 1 10 f
X AGND 1 100 -1600 100 U 50 50 1 1 W
X REFOUT 2 900 700 100 L 50 50 1 1 O
@ -134,7 +149,7 @@ X DVDD 9 -100 1600 100 D 50 50 1 1 P N
X FSELECT 10 -900 1200 100 R 50 50 1 1 I
X DB9 20 -900 -100 100 R 50 50 1 1 I
X DB1 30 -900 700 100 R 50 50 1 1 I
X FS_ADJUST 40 900 -1200 100 L 50 50 1 1 P
X FS_ADJUST 40 900 -500 100 L 50 50 1 1 P
X PSEL0 11 -900 1100 100 R 50 50 1 1 I
X DB8 21 -900 0 100 R 50 50 1 1 I
X DB0 31 -900 800 100 R 50 50 1 1 I
@ -170,6 +185,7 @@ X NC 48 800 -400 100 L 50 50 1 1 N N
X DB10 19 -900 -200 100 R 50 50 1 1 I
X DGND 29 -100 -1600 100 U 50 50 1 1 P N
X IOUT 39 900 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
@ -185,6 +201,28 @@ $FPLIST
TQFP*14x14mm*Pitch0.65mm*
$ENDFPLIST
DRAW
T 900 -50 50 60 0 0 0 CLOCKING~AND~CONTROL Normal 0 C C
T 0 300 -100 60 0 0 0 CONTROL Normal 0 C C
T 0 250 600 60 0 0 0 CORE Normal 0 C C
T 0 300 300 60 0 0 0 COSINE Normal 0 C C
T 0 300 -200 60 0 0 0 DAC Normal 0 C C
T 0 300 200 60 0 0 0 DAC Normal 0 C C
T 900 -400 400 60 0 0 0 DATA Normal 0 C C
T 0 250 700 60 0 0 0 DDS Normal 0 C C
T 900 -300 400 60 0 0 0 INTERFACE Normal 0 C C
T 900 -500 400 60 0 0 0 PARALLEL Normal 0 C C
T 900 -600 400 60 0 0 0 SERIAL/ Normal 0 C C
S 400 800 100 500 0 0 0 N
P 2 0 0 0 -250 250 -150 250 N
P 2 0 0 0 100 -150 0 -150 N
P 2 0 0 0 100 250 0 250 N
P 2 0 0 0 250 500 250 400 N
P 3 0 0 0 250 800 250 900 0 900 N
P 4 0 0 0 -800 -550 -150 -550 -150 1150 -800 1150 N
P 4 0 0 0 -800 1050 -250 1050 -250 -450 -800 -450 N
P 5 0 0 0 -800 -1150 0 -1150 0 1250 -250 1250 -250 1500 N
P 6 0 0 0 550 -150 400 0 100 0 100 -300 400 -300 550 -150 N
P 6 0 0 0 550 250 400 400 100 400 100 100 400 100 550 250 N
S -800 1500 800 -1500 0 1 10 f
X D7 1 -900 300 100 R 50 50 1 1 I
X D6 2 -900 400 100 R 50 50 1 1 I
@ -255,17 +293,18 @@ X DGND 77 -100 -1600 100 U 50 50 1 1 P N
X A1/SDO 18 -900 0 100 R 50 50 1 1 B
X DGND 28 -100 -1600 100 U 50 50 1 1 P N
X AVDD 38 100 1600 100 D 50 50 1 1 P N
X IOUT1 48 900 200 100 L 50 50 1 1 O
X IOUT1 48 900 300 100 L 50 50 1 1 O
X NC 58 900 900 100 L 50 50 1 1 N N
X ~REFCLK 68 -900 1300 100 R 50 50 1 1 I
X DGND 78 -100 -1600 100 U 50 50 1 1 P N
X A0/SDIO 19 -900 100 100 R 50 50 1 1 B
X FSK/BPSK/HOLD 29 -900 -1000 100 R 50 50 1 1 I
X AGND 39 100 -1600 100 U 50 50 1 1 P N
X ~IOUT1 49 900 100 100 L 50 50 1 1 O
X ~IOUT1 49 900 200 100 L 50 50 1 1 O
X AGND 59 100 -1600 100 U 50 50 1 1 P N
X REFCLK 69 -900 1400 100 R 50 50 1 1 I
X DVDD 79 -100 1600 100 D 50 50 1 1 P N
ENDDRAW
ENDDEF
#
@ -281,6 +320,28 @@ $FPLIST
TQFP*EP*14x14mm*Pitch0.65mm*
$ENDFPLIST
DRAW
T 900 -50 50 60 0 0 0 CLOCKING~AND~CONTROL Normal 0 C C
T 0 300 -100 60 0 0 0 CONTROL Normal 0 C C
T 0 250 600 60 0 0 0 CORE Normal 0 C C
T 0 300 300 60 0 0 0 COSINE Normal 0 C C
T 0 300 -200 60 0 0 0 DAC Normal 0 C C
T 0 300 200 60 0 0 0 DAC Normal 0 C C
T 900 -400 400 60 0 0 0 DATA Normal 0 C C
T 0 250 700 60 0 0 0 DDS Normal 0 C C
T 900 -300 400 60 0 0 0 INTERFACE Normal 0 C C
T 900 -500 400 60 0 0 0 PARALLEL Normal 0 C C
T 900 -600 400 60 0 0 0 SERIAL/ Normal 0 C C
S 400 800 100 500 0 0 0 N
P 2 0 0 0 -250 250 -150 250 N
P 2 0 0 0 100 -150 0 -150 N
P 2 0 0 0 100 250 0 250 N
P 2 0 0 0 250 500 250 400 N
P 3 0 0 0 250 800 250 900 0 900 N
P 4 0 0 0 -800 -550 -150 -550 -150 1150 -800 1150 N
P 4 0 0 0 -800 1050 -250 1050 -250 -450 -800 -450 N
P 5 0 0 0 -800 -1150 0 -1150 0 1250 -250 1250 -250 1500 N
P 6 0 0 0 550 -150 400 0 100 0 100 -300 400 -300 550 -150 N
P 6 0 0 0 550 250 400 400 100 400 100 100 400 100 550 250 N
S -800 1500 800 -1500 0 1 10 f
X D7 1 -900 300 100 R 50 50 1 1 I
X D6 2 -900 400 100 R 50 50 1 1 I
@ -352,17 +413,18 @@ X DGND 77 -100 -1600 100 U 50 50 1 1 P N
X A1/SDO 18 -900 0 100 R 50 50 1 1 B
X DGND 28 -100 -1600 100 U 50 50 1 1 P N
X AVDD 38 100 1600 100 D 50 50 1 1 P N
X IOUT1 48 900 200 100 L 50 50 1 1 O
X IOUT1 48 900 300 100 L 50 50 1 1 O
X NC 58 900 900 100 L 50 50 1 1 N N
X ~REFCLK 68 -900 1300 100 R 50 50 1 1 I
X DGND 78 -100 -1600 100 U 50 50 1 1 P N
X A0/SDIO 19 -900 100 100 R 50 50 1 1 B
X FSK/BPSK/HOLD 29 -900 -1000 100 R 50 50 1 1 I
X AGND 39 100 -1600 100 U 50 50 1 1 P N
X ~IOUT1 49 900 100 100 L 50 50 1 1 O
X ~IOUT1 49 900 200 100 L 50 50 1 1 O
X AGND 59 100 -1600 100 U 50 50 1 1 P N
X REFCLK 69 -900 1400 100 R 50 50 1 1 I
X DVDD 79 -100 1600 100 D 50 50 1 1 P N
ENDDRAW
ENDDEF
#
@ -377,6 +439,45 @@ $FPLIST
TQFP*14x14mm*Pitch0.5mm*
$ENDFPLIST
DRAW
T 0 150 500 60 0 0 0 1024- Normal 0 C C
T 0 150 -650 60 0 0 0 1GBPS Normal 0 C C
T 0 150 -1300 60 0 0 0 AND Normal 0 C C
T 0 150 -1400 60 0 0 0 CONTROL Normal 0 C C
T 0 150 -850 60 0 0 0 CORE Normal 0 C C
T 0 650 -800 60 0 0 0 DAC Normal 0 C C
T 900 -500 -1300 60 0 0 0 DATA Normal 0 C C
T 0 150 -750 60 0 0 0 DDS Normal 0 C C
T 0 150 400 60 0 0 0 ELEMENT Normal 0 C C
T 0 150 -250 60 0 0 0 GENERATOR Normal 0 C C
T 900 -625 0 60 0 0 0 HIGH~SPEED Normal 0 C C
T 900 -425 0 60 0 0 0 INTERFACE Normal 0 C C
T 900 -400 -1300 60 0 0 0 INTERFACE Normal 0 C C
T 0 150 -50 60 0 0 0 LINEAR Normal 0 C C
T 0 150 -1950 60 0 0 0 MULTIPLIER Normal 0 C C
T 900 -525 0 60 0 0 0 PARALLEL~DATA Normal 0 C C
T 0 150 300 60 0 0 0 RAM Normal 0 C C
T 0 150 -150 60 0 0 0 RAMP Normal 0 C C
T 0 150 -1850 60 0 0 0 REFCLK Normal 0 C C
T 900 -600 -1275 60 0 0 0 SERIAL Normal 0 C C
T 0 150 -1200 60 0 0 0 TIMING Normal 0 C C
S -100 -1100 400 -1500 0 0 0 N
S -100 600 400 200 0 0 0 N
S 350 -550 -50 -950 0 0 0 N
S 450 -350 -150 50 0 0 0 N
P 2 0 0 0 -100 -1300 -350 -1300 N
P 2 0 0 0 -50 -750 -350 -750 N
P 2 0 0 0 50 -550 50 -350 N
P 2 0 0 0 150 -1500 150 -1750 N
P 2 0 0 0 150 -950 150 -1100 N
P 2 0 0 0 450 -750 350 -750 N
P 2 0 0 0 850 -800 900 -800 N
P 2 0 0 0 900 -700 850 -700 N
P 4 0 0 0 -1100 -1050 -350 -1050 -350 -1550 -1100 -1550 N
P 4 0 0 0 -1100 950 -350 950 -350 -950 -1100 -950 N
P 5 0 0 0 400 400 600 400 600 -450 250 -450 250 -550 N
P 6 0 0 0 900 -750 750 -600 450 -600 450 -900 750 -900 900 -750 N
P 7 0 0 0 -400 -2400 -400 -2150 450 -2150 450 -1750 -150 -1750 -150 -1950 -1100 -1950 N
T 0 650 -700 60 0 1 0 14-BIT Normal 0 C C
S -1100 2400 1100 -2400 0 1 10 f
X NC 1 1100 1900 100 L 50 50 1 1 N N
X PLL_LOOP_FILTER 2 -1200 -2000 100 R 50 50 1 1 I
@ -391,50 +492,50 @@ X SYNC_OUT- 10 1200 2100 100 L 50 50 1 1 O
X NC 20 1100 1800 100 L 50 50 1 1 N N
X DVDD_1V8 30 100 2500 100 D 50 50 1 1 P N
X PDCLK 40 1200 -100 100 L 50 50 1 1 O
X F0 50 -1200 -100 100 R 50 50 1 1 I
X F0 50 -1200 800 100 R 50 50 1 1 I
X OSK 60 -1200 1300 100 R 50 50 1 1 I
X ~CS 70 -1200 600 100 R 50 50 1 1 I
X ~CS 70 -1200 -1400 100 R 50 50 1 1 I
X ~IOUT 80 1200 -700 100 L 50 50 1 1 O
X REF_CLK 90 -1200 -2100 100 R 50 50 1 1 I
X DVDD_IO_3V3 11 300 2500 100 D 50 50 1 1 W
X DVDD_IO_3V3 21 300 2500 100 D 50 50 1 1 P N
X D12 31 -1200 -1500 100 R 50 50 1 1 I
X TxENABLE 41 -1200 0 100 R 50 50 1 1 I
X D12 31 -1200 -600 100 R 50 50 1 1 I
X TxENABLE 41 -1200 900 100 R 50 50 1 1 I
X DGND 51 200 -2500 100 U 50 50 1 1 P N
X DROVER 61 1200 200 100 L 50 50 1 1 O
X I/O_RESET 71 -1200 500 100 R 50 50 1 1 I
X I/O_RESET 71 -1200 -1500 100 R 50 50 1 1 I
X IOUT 81 1200 -800 100 L 50 50 1 1 O
X ~REF_CLK 91 -1200 -2200 100 R 50 50 1 1 I
X SYNC_SMP_ERR 12 1200 2000 100 L 50 50 1 1 O
X DGND 22 200 -2500 100 U 50 50 1 1 P N
X D11 32 -1200 -1400 100 R 50 50 1 1 I
X D3 42 -1200 -600 100 R 50 50 1 1 I
X D11 32 -1200 -500 100 R 50 50 1 1 I
X D3 42 -1200 300 100 R 50 50 1 1 I
X PROFILE2 52 -1200 1500 100 R 50 50 1 1 I
X DRCTL 62 -1200 300 100 R 50 50 1 1 I
X DRCTL 62 -1200 -1700 100 R 50 50 1 1 I
X NC 72 1100 1700 100 L 50 50 1 1 N N
X AGND 82 -200 -2500 100 U 50 50 1 1 P N
X AVDD_1V8 92 -300 2500 100 D 50 50 1 1 P N
X DGND 13 200 -2500 100 U 50 50 1 1 W
X DVDD_1V8 23 100 2500 100 D 50 50 1 1 P N
X D10 33 -1200 -1300 100 R 50 50 1 1 I
X D2 43 -1200 -500 100 R 50 50 1 1 I
X D10 33 -1200 -400 100 R 50 50 1 1 I
X D2 43 -1200 400 100 R 50 50 1 1 I
X PROFILE1 53 -1200 1600 100 R 50 50 1 1 I
X DRHOLD 63 -1200 200 100 R 50 50 1 1 I
X DRHOLD 63 -1200 -1800 100 R 50 50 1 1 I
X AGND 73 -200 -2500 100 U 50 50 1 1 P N
X AVDD_3V3 83 -100 2500 100 D 50 50 1 1 P N
X NC 93 1100 1400 100 L 50 50 1 1 N N
X MASTER_RESET 14 -1200 2000 100 R 50 50 1 1 I
X RAM_SWP_OVR 24 1200 1200 100 L 50 50 1 1 O
X D9 34 -1200 -1200 100 R 50 50 1 1 I
X D1 44 -1200 -400 100 R 50 50 1 1 I
X D9 34 -1200 -300 100 R 50 50 1 1 I
X D1 44 -1200 500 100 R 50 50 1 1 I
X PROFILE0 54 -1200 1700 100 R 50 50 1 1 I
X DVDD_1V8 64 100 2500 100 D 50 50 1 1 P N
X AVDD_3V3 74 -100 2500 100 D 50 50 1 1 W
X DAC_RSET 84 1200 -1300 100 L 50 50 1 1 O
X REFCLK_OUT 94 1200 -2300 100 L 50 50 1 1 O
X DVDD_IO_3V3 15 300 2500 100 D 50 50 1 1 P N
X D15 25 -1200 -1800 100 R 50 50 1 1 I
X D8 35 -1200 -1100 100 R 50 50 1 1 I
X D15 25 -1200 -900 100 R 50 50 1 1 I
X D8 35 -1200 -200 100 R 50 50 1 1 I
X DVDD_IO_3V3 45 300 2500 100 D 50 50 1 1 P N
X SYNC_CLK 55 1200 -2100 100 L 50 50 1 1 O
X DGND 65 200 -2500 100 U 50 50 1 1 P N
@ -442,8 +543,8 @@ X AVDD_3V3 75 -100 2500 100 D 50 50 1 1 P N
X AGND 85 -200 -2500 100 U 50 50 1 1 P N
X XTAL_SEL 95 -1200 -2300 100 R 50 50 1 1 I
X DGND 16 200 -2500 100 U 50 50 1 1 P N
X D14 26 -1200 -1700 100 R 50 50 1 1 I
X D7 36 -1200 -1000 100 R 50 50 1 1 I
X D14 26 -1200 -800 100 R 50 50 1 1 I
X D7 36 -1200 -100 100 R 50 50 1 1 I
X DGND 46 200 -2500 100 U 50 50 1 1 P N
X DVDD_IO_3V3 56 300 2500 100 D 50 50 1 1 P N
X DVDD_IO_3V3 66 300 2500 100 D 50 50 1 1 P N
@ -451,34 +552,35 @@ X AVDD_3V3 76 -100 2500 100 D 50 50 1 1 P N
X NC 86 1100 1600 100 L 50 50 1 1 N N
X AGND 96 -200 -2500 100 U 50 50 1 1 P N
X DVDD_1V8 17 100 2500 100 D 50 50 1 1 W
X D13 27 -1200 -1600 100 R 50 50 1 1 I
X D6 37 -1200 -900 100 R 50 50 1 1 I
X D13 27 -1200 -700 100 R 50 50 1 1 I
X D6 37 -1200 0 100 R 50 50 1 1 I
X DVDD_1V8 47 100 2500 100 D 50 50 1 1 P N
X DVDD_1V8 57 100 2500 100 D 50 50 1 1 P N
X SDIO 67 -1200 800 100 R 50 50 1 1 B
X SDIO 67 -1200 -1200 100 R 50 50 1 1 B
X AVDD_3V3 77 -100 2500 100 D 50 50 1 1 P N
X NC 87 1100 1500 100 L 50 50 1 1 N N
X NC 97 1100 1300 100 L 50 50 1 1 N N
X EXT_PWR_DWN 18 -1200 1900 100 R 50 50 1 1 I
X DVDD_IO_3V3 28 300 2500 100 D 50 50 1 1 P N
X D5 38 -1200 -800 100 R 50 50 1 1 I
X D0 48 -1200 -300 100 R 50 50 1 1 I
X D5 38 -1200 100 100 R 50 50 1 1 I
X D0 48 -1200 600 100 R 50 50 1 1 I
X DGND 58 200 -2500 100 U 50 50 1 1 P N
X SDO 68 -1200 700 100 R 50 50 1 1 O
X SDO 68 -1200 -1300 100 R 50 50 1 1 O
X AGND 78 -200 -2500 100 U 50 50 1 1 P N
X AGND 88 -200 -2500 100 U 50 50 1 1 P N
X NC 98 1100 1100 100 L 50 50 1 1 N N
X PLL_LOCK 19 1200 -1900 100 L 50 50 1 1 O
X DGND 29 200 -2500 100 U 50 50 1 1 P N
X D4 39 -1200 -700 100 R 50 50 1 1 I
X F1 49 -1200 -200 100 R 50 50 1 1 I
X D4 39 -1200 200 100 R 50 50 1 1 I
X F1 49 -1200 700 100 R 50 50 1 1 I
X I/O_UPDATE 59 -1200 1100 100 R 50 50 1 1 B
X SCLK 69 -1200 900 100 R 50 50 1 1 I
X SCLK 69 -1200 -1100 100 R 50 50 1 1 I
X AGND 79 -200 -2500 100 U 50 50 1 1 P N
X AVDD_1V8 89 -300 2500 100 D 50 50 1 1 P N
X NC 99 1100 1000 100 L 50 50 1 1 N N
X NC 100 1100 900 100 L 50 50 1 1 N N
X EP 101 0 -2500 100 U 50 50 1 1 W
ENDDRAW
ENDDEF
#