Incorporated feedback.
1. Updated socket strip footprint. 2. Moved socket strip to bottom of board, pin 1 inward. 3. Corrected pinout. 4. 5. removed unused libraries.
This commit is contained in:
ashtonchase
parent
094eb89b64
commit
7c89fb0ac2
5 changed files with 414 additions and 592 deletions
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@ -1,15 +1,15 @@
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(kicad_pcb (version 20160815) (host pcbnew 201611191051+7361~55~ubuntu16.04.1-product)
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(kicad_pcb (version 20170123) (host pcbnew "(2017-02-21 revision 35a8d78)-master")
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||||
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||||
(general
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||||
(links 10)
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||||
(no_connects 10)
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||||
(area 199.949999 93.949999 265.050001 150.050001)
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||||
(links 9)
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||||
(no_connects 9)
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||||
(area 199.949999 88.772619 287.050001 168.05)
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||||
(thickness 1.6)
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||||
(drawings 39)
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||||
(tracks 0)
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(zones 0)
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(modules 5)
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(nets 31)
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(nets 32)
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)
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(page A3)
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@ -97,29 +97,30 @@
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(net 5 /ID_SC)
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(net 6 /GPIO5)
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(net 7 /GPIO6)
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(net 8 /GPIO12)
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(net 9 /GPIO13)
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(net 10 /GPIO19)
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(net 11 /GPIO20)
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(net 12 /GPIO26)
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(net 13 /GPIO21)
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(net 14 "/GPIO2(SDA1)")
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(net 15 "/GPIO3(SCL1)")
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(net 16 "/GPIO4(GCLK)")
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(net 17 "/GPIO14(TXD0)")
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(net 18 "/GPIO15(RXD0)")
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(net 19 "/GPIO17(GEN0)")
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(net 20 "/GPIO18(GEN1)")
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(net 21 "/GPIO27(GEN2)")
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(net 22 "/GPIO22(GEN3)")
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(net 23 "/GPIO23(GEN4)")
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(net 24 "/GPIO24(GEN5)")
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(net 25 "/GPIO10(SPI_MOSI)")
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(net 26 "/GPIO9(SPI_MISO)")
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(net 27 "/GPIO25(GEN6)")
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(net 28 "/GPIO11(SPI_CLK)")
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(net 29 "/GPIO8(SPI_CE0_N)")
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(net 30 "/GPIO7(SPI_CE1_N)")
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(net 8 /GPIO26)
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(net 9 "/GPIO2(SDA1)")
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(net 10 "/GPIO3(SCL1)")
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(net 11 "/GPIO4(GCLK)")
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(net 12 "/GPIO14(TXD0)")
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(net 13 "/GPIO15(RXD0)")
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(net 14 "/GPIO17(GEN0)")
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(net 15 "/GPIO27(GEN2)")
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(net 16 "/GPIO22(GEN3)")
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(net 17 "/GPIO23(GEN4)")
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(net 18 "/GPIO24(GEN5)")
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(net 19 "/GPIO25(GEN6)")
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(net 20 "/GPIO18(GEN1)(PWM0)")
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(net 21 "/GPIO10(SPI0_MOSI)")
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(net 22 "/GPIO9(SPI0_MISO)")
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(net 23 "/GPIO11(SPI0_SCK)")
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(net 24 "/GPIO8(SPI0_CE_N)")
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(net 25 "/GPIO7(SPI1_CE_N)")
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(net 26 "/GPIO12(PWM0)")
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(net 27 "/GPIO13(PWM1)")
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(net 28 "/GPIO19(SPI1_MISO)")
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(net 29 /GPIO16)
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(net 30 "/GPIO20(SPI1_MOSI)")
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(net 31 "/GPIO21(SPI1_SCK)")
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(net_class Default "This is the default net class."
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(clearance 0.2)
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@ -128,22 +129,21 @@
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(via_drill 0.6)
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(uvia_dia 0.5)
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(uvia_drill 0.1)
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(diff_pair_gap 0.25)
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(diff_pair_width 0.2)
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(add_net +3V3)
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(add_net +5V)
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(add_net "/GPIO10(SPI_MOSI)")
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(add_net "/GPIO11(SPI_CLK)")
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(add_net /GPIO12)
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(add_net /GPIO13)
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(add_net "/GPIO10(SPI0_MOSI)")
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(add_net "/GPIO11(SPI0_SCK)")
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(add_net "/GPIO12(PWM0)")
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(add_net "/GPIO13(PWM1)")
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(add_net "/GPIO14(TXD0)")
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(add_net "/GPIO15(RXD0)")
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(add_net /GPIO16)
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(add_net "/GPIO17(GEN0)")
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(add_net "/GPIO18(GEN1)")
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(add_net /GPIO19)
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(add_net "/GPIO18(GEN1)(PWM0)")
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(add_net "/GPIO19(SPI1_MISO)")
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(add_net "/GPIO2(SDA1)")
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(add_net /GPIO20)
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(add_net /GPIO21)
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(add_net "/GPIO20(SPI1_MOSI)")
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(add_net "/GPIO21(SPI1_SCK)")
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(add_net "/GPIO22(GEN3)")
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(add_net "/GPIO23(GEN4)")
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(add_net "/GPIO24(GEN5)")
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@ -154,9 +154,9 @@
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(add_net "/GPIO4(GCLK)")
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(add_net /GPIO5)
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(add_net /GPIO6)
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(add_net "/GPIO7(SPI_CE1_N)")
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(add_net "/GPIO8(SPI_CE0_N)")
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(add_net "/GPIO9(SPI_MISO)")
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(add_net "/GPIO7(SPI1_CE_N)")
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(add_net "/GPIO8(SPI0_CE_N)")
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(add_net "/GPIO9(SPI0_MISO)")
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(add_net /ID_SC)
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(add_net /ID_SD)
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(add_net GND)
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@ -169,8 +169,123 @@
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(via_drill 0.7)
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(uvia_dia 0.5)
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(uvia_drill 0.1)
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(diff_pair_gap 0.25)
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(diff_pair_width 0.2)
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)
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(module Socket_Strips:Socket_Strip_Straight_2x20_Pitch2.54mm (layer B.Cu) (tedit 58CD544A) (tstamp 580C7F66)
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(at 208.37 98.77 270)
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(descr "Through hole straight socket strip, 2x20, 2.54mm pitch, double rows")
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(tags "Through hole socket strip THT 2x20 2.54mm double row")
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(path /59AD464A)
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(fp_text reference P1 (at 2.208 -0.012 180) (layer B.SilkS)
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(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
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)
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(fp_text value Conn_02x20_Odd_Even (at -1.27 -50.59 270) (layer B.Fab)
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(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
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)
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(fp_line (start -3.81 1.27) (end -3.81 -49.53) (layer B.Fab) (width 0.1))
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(fp_line (start -3.81 -49.53) (end 1.27 -49.53) (layer B.Fab) (width 0.1))
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(fp_line (start 1.27 -49.53) (end 1.27 1.27) (layer B.Fab) (width 0.1))
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(fp_line (start 1.27 1.27) (end -3.81 1.27) (layer B.Fab) (width 0.1))
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(fp_line (start 1.33 -1.27) (end 1.33 -49.59) (layer B.SilkS) (width 0.12))
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(fp_line (start 1.33 -49.59) (end -3.87 -49.59) (layer B.SilkS) (width 0.12))
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(fp_line (start -3.87 -49.59) (end -3.87 1.33) (layer B.SilkS) (width 0.12))
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(fp_line (start -3.87 1.33) (end -1.27 1.33) (layer B.SilkS) (width 0.12))
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(fp_line (start -1.27 1.33) (end -1.27 -1.27) (layer B.SilkS) (width 0.12))
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(fp_line (start -1.27 -1.27) (end 1.33 -1.27) (layer B.SilkS) (width 0.12))
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(fp_line (start 1.33 0) (end 1.33 1.33) (layer B.SilkS) (width 0.12))
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(fp_line (start 1.33 1.33) (end 0.06 1.33) (layer B.SilkS) (width 0.12))
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(fp_line (start -4.35 1.8) (end -4.35 -50.05) (layer B.CrtYd) (width 0.05))
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(fp_line (start -4.35 -50.05) (end 1.8 -50.05) (layer B.CrtYd) (width 0.05))
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(fp_line (start 1.8 -50.05) (end 1.8 1.8) (layer B.CrtYd) (width 0.05))
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(fp_line (start 1.8 1.8) (end -4.35 1.8) (layer B.CrtYd) (width 0.05))
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||||
(fp_text user %R (at -1.27 2.33 270) (layer B.Fab)
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(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
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)
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(pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 1 +3V3))
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(pad 2 thru_hole oval (at -2.54 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 2 +5V))
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(pad 3 thru_hole oval (at 0 -2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 9 "/GPIO2(SDA1)"))
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(pad 4 thru_hole oval (at -2.54 -2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 2 +5V))
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(pad 5 thru_hole oval (at 0 -5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 10 "/GPIO3(SCL1)"))
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(pad 6 thru_hole oval (at -2.54 -5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 3 GND))
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(pad 7 thru_hole oval (at 0 -7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 11 "/GPIO4(GCLK)"))
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(pad 8 thru_hole oval (at -2.54 -7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 12 "/GPIO14(TXD0)"))
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(pad 9 thru_hole oval (at 0 -10.16 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 3 GND))
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(pad 10 thru_hole oval (at -2.54 -10.16 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 13 "/GPIO15(RXD0)"))
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(pad 11 thru_hole oval (at 0 -12.7 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 14 "/GPIO17(GEN0)"))
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(pad 12 thru_hole oval (at -2.54 -12.7 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 20 "/GPIO18(GEN1)(PWM0)"))
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(pad 13 thru_hole oval (at 0 -15.24 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 15 "/GPIO27(GEN2)"))
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(pad 14 thru_hole oval (at -2.54 -15.24 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 3 GND))
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(pad 15 thru_hole oval (at 0 -17.78 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 16 "/GPIO22(GEN3)"))
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(pad 16 thru_hole oval (at -2.54 -17.78 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 17 "/GPIO23(GEN4)"))
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(pad 17 thru_hole oval (at 0 -20.32 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 1 +3V3))
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(pad 18 thru_hole oval (at -2.54 -20.32 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 18 "/GPIO24(GEN5)"))
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(pad 19 thru_hole oval (at 0 -22.86 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 21 "/GPIO10(SPI0_MOSI)"))
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(pad 20 thru_hole oval (at -2.54 -22.86 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 3 GND))
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(pad 21 thru_hole oval (at 0 -25.4 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 22 "/GPIO9(SPI0_MISO)"))
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(pad 22 thru_hole oval (at -2.54 -25.4 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 19 "/GPIO25(GEN6)"))
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(pad 23 thru_hole oval (at 0 -27.94 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 23 "/GPIO11(SPI0_SCK)"))
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(pad 24 thru_hole oval (at -2.54 -27.94 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 24 "/GPIO8(SPI0_CE_N)"))
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(pad 25 thru_hole oval (at 0 -30.48 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 3 GND))
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(pad 26 thru_hole oval (at -2.54 -30.48 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 25 "/GPIO7(SPI1_CE_N)"))
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(pad 27 thru_hole oval (at 0 -33.02 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 4 /ID_SD))
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(pad 28 thru_hole oval (at -2.54 -33.02 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 5 /ID_SC))
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(pad 29 thru_hole oval (at 0 -35.56 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 6 /GPIO5))
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(pad 30 thru_hole oval (at -2.54 -35.56 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 3 GND))
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(pad 31 thru_hole oval (at 0 -38.1 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 7 /GPIO6))
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||||
(pad 32 thru_hole oval (at -2.54 -38.1 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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||||
(net 26 "/GPIO12(PWM0)"))
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||||
(pad 33 thru_hole oval (at 0 -40.64 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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||||
(net 27 "/GPIO13(PWM1)"))
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(pad 34 thru_hole oval (at -2.54 -40.64 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 3 GND))
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(pad 35 thru_hole oval (at 0 -43.18 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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||||
(net 28 "/GPIO19(SPI1_MISO)"))
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(pad 36 thru_hole oval (at -2.54 -43.18 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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||||
(net 29 /GPIO16))
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(pad 37 thru_hole oval (at 0 -45.72 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 8 /GPIO26))
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(pad 38 thru_hole oval (at -2.54 -45.72 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 30 "/GPIO20(SPI1_MOSI)"))
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(pad 39 thru_hole oval (at 0 -48.26 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 3 GND))
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(pad 40 thru_hole oval (at -2.54 -48.26 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(net 31 "/GPIO21(SPI1_SCK)"))
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(model ${KISYS3DMOD}/Socket_Strips.3dshapes/Socket_Strip_Straight_2x20_Pitch2.54mm.wrl
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(at (xyz -0.05 -0.95 0))
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||||
(scale (xyz 1 1 1))
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(rotate (xyz 0 0 270))
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)
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)
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(module Mounting_Holes:MountingHole_2-5mm (layer F.Cu) (tedit 5834FC00) (tstamp 580CBA7A)
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||||
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@ -221,116 +336,6 @@
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(solder_mask_margin 1.25) (clearance 1.35))
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||||
)
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||||
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||||
(module Socket_Strips:Socket_Strip_Straight_2x20 (layer F.Cu) (tedit 580C0D63) (tstamp 580C7F66)
|
||||
(at 208.37 96.23)
|
||||
(descr "Through hole socket strip")
|
||||
(tags "socket strip")
|
||||
(path /580C18BB)
|
||||
(fp_text reference P1 (at 0 5.002) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value CONN_02X20 (at 0 -3.1) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start -1.75 -1.75) (end -1.75 4.3) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 50.05 -1.75) (end 50.05 4.3) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.75 -1.75) (end 50.05 -1.75) (layer F.CrtYd) (width 0.05))
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||||
(fp_line (start -1.75 4.3) (end 50.05 4.3) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 49.53 3.81) (end -1.27 3.81) (layer F.SilkS) (width 0.15))
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||||
(fp_line (start 1.27 -1.27) (end 49.53 -1.27) (layer F.SilkS) (width 0.15))
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||||
(fp_line (start 49.53 3.81) (end 49.53 -1.27) (layer F.SilkS) (width 0.15))
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||||
(fp_line (start -1.27 3.81) (end -1.27 1.27) (layer F.SilkS) (width 0.15))
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||||
(fp_line (start 0 -1.55) (end -1.55 -1.55) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -1.27 1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.15))
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||||
(fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15))
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||||
(fp_line (start -1.55 -1.55) (end -1.55 0) (layer F.SilkS) (width 0.15))
|
||||
(pad 1 thru_hole rect (at 0 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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||||
(net 1 +3V3))
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||||
(pad 2 thru_hole oval (at 0 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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||||
(net 2 +5V))
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||||
(pad 3 thru_hole oval (at 2.54 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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||||
(net 14 "/GPIO2(SDA1)"))
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||||
(pad 4 thru_hole oval (at 2.54 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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||||
(net 2 +5V))
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||||
(pad 5 thru_hole oval (at 5.08 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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||||
(net 15 "/GPIO3(SCL1)"))
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||||
(pad 6 thru_hole oval (at 5.08 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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||||
(net 3 GND))
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||||
(pad 7 thru_hole oval (at 7.62 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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||||
(net 16 "/GPIO4(GCLK)"))
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||||
(pad 8 thru_hole oval (at 7.62 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 17 "/GPIO14(TXD0)"))
|
||||
(pad 9 thru_hole oval (at 10.16 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 3 GND))
|
||||
(pad 10 thru_hole oval (at 10.16 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 18 "/GPIO15(RXD0)"))
|
||||
(pad 11 thru_hole oval (at 12.7 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 19 "/GPIO17(GEN0)"))
|
||||
(pad 12 thru_hole oval (at 12.7 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 20 "/GPIO18(GEN1)"))
|
||||
(pad 13 thru_hole oval (at 15.24 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 21 "/GPIO27(GEN2)"))
|
||||
(pad 14 thru_hole oval (at 15.24 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 3 GND))
|
||||
(pad 15 thru_hole oval (at 17.78 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 22 "/GPIO22(GEN3)"))
|
||||
(pad 16 thru_hole oval (at 17.78 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 23 "/GPIO23(GEN4)"))
|
||||
(pad 17 thru_hole oval (at 20.32 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 1 +3V3))
|
||||
(pad 18 thru_hole oval (at 20.32 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 24 "/GPIO24(GEN5)"))
|
||||
(pad 19 thru_hole oval (at 22.86 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 25 "/GPIO10(SPI_MOSI)"))
|
||||
(pad 20 thru_hole oval (at 22.86 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 3 GND))
|
||||
(pad 21 thru_hole oval (at 25.4 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 26 "/GPIO9(SPI_MISO)"))
|
||||
(pad 22 thru_hole oval (at 25.4 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 27 "/GPIO25(GEN6)"))
|
||||
(pad 23 thru_hole oval (at 27.94 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 28 "/GPIO11(SPI_CLK)"))
|
||||
(pad 24 thru_hole oval (at 27.94 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 29 "/GPIO8(SPI_CE0_N)"))
|
||||
(pad 25 thru_hole oval (at 30.48 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 3 GND))
|
||||
(pad 26 thru_hole oval (at 30.48 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 30 "/GPIO7(SPI_CE1_N)"))
|
||||
(pad 27 thru_hole oval (at 33.02 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 4 /ID_SD))
|
||||
(pad 28 thru_hole oval (at 33.02 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 5 /ID_SC))
|
||||
(pad 29 thru_hole oval (at 35.56 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 6 /GPIO5))
|
||||
(pad 30 thru_hole oval (at 35.56 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 3 GND))
|
||||
(pad 31 thru_hole oval (at 38.1 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 7 /GPIO6))
|
||||
(pad 32 thru_hole oval (at 38.1 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 8 /GPIO12))
|
||||
(pad 33 thru_hole oval (at 40.64 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 9 /GPIO13))
|
||||
(pad 34 thru_hole oval (at 40.64 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 3 GND))
|
||||
(pad 35 thru_hole oval (at 43.18 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 10 /GPIO19))
|
||||
(pad 36 thru_hole oval (at 43.18 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 11 /GPIO20))
|
||||
(pad 37 thru_hole oval (at 45.72 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 12 /GPIO26))
|
||||
(pad 38 thru_hole oval (at 45.72 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 13 /GPIO21))
|
||||
(pad 39 thru_hole oval (at 48.26 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 3 GND))
|
||||
(pad 40 thru_hole oval (at 48.26 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 3 GND))
|
||||
(model Socket_Strips.3dshapes/Socket_Strip_Straight_2x20.wrl
|
||||
(at (xyz 0.95 -0.05 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 180))
|
||||
)
|
||||
)
|
||||
|
||||
(module Mounting_Holes:MountingHole_2-5mm (layer F.Cu) (tedit 5834FC15) (tstamp 580CBAD7)
|
||||
(at 261.5 146.5)
|
||||
(descr "Mounting hole, Befestigungsbohrung, 2,5mm, No Annular, Kein Restring,")
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue