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Template Arduino : Fix pin order SS, MOSI, MISO, SCK

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This commit is contained in:
Ashton Johnson 2017-01-17 20:19:36 -06:00
parent aa251244fa
commit 5f329e7646
11 changed files with 129 additions and 128 deletions
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82
template/Arduino_Nano/Arduino_Nano.kicad_pcb
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@ -1,4 +1,4 @@
(kicad_pcb (version 4) (host pcbnew 4.0.2-4+6225~38~ubuntu14.04.1-stable)
(kicad_pcb (version 4) (host pcbnew 4.0.4+e1-6308~48~ubuntu14.04.1-stable)
(general
(links 2)
@ -108,25 +108,25 @@
(net 11 /8)
(net 12 "/9(**)")
(net 13 "/10(**/SS)")
(net 14 "/11(**/MISO)")
(net 15 "/12(MOSI)")
(net 16 /Vin)
(net 17 +5V)
(net 18 /A7)
(net 19 /A6)
(net 20 /A5)
(net 21 /A4)
(net 22 /A3)
(net 23 /A2)
(net 24 /A1)
(net 25 /A0)
(net 26 /AREF)
(net 27 "/13(SCK)")
(net 28 "Net-(P3-Pad1)")
(net 29 "Net-(P4-Pad1)")
(net 30 "Net-(P5-Pad1)")
(net 31 "Net-(P6-Pad1)")
(net 32 +3V3)
(net 14 /Vin)
(net 15 +5V)
(net 16 /A7)
(net 17 /A6)
(net 18 /A5)
(net 19 /A4)
(net 20 /A3)
(net 21 /A2)
(net 22 /A1)
(net 23 /A0)
(net 24 /AREF)
(net 25 "/13(SCK)")
(net 26 "Net-(P3-Pad1)")
(net 27 "Net-(P4-Pad1)")
(net 28 "Net-(P5-Pad1)")
(net 29 "Net-(P6-Pad1)")
(net 30 +3V3)
(net 31 "/11(**/MOSI)")
(net 32 "/12(MISO)")
(net_class Default "This is the default net class."
(clearance 0.2)
@ -140,8 +140,8 @@
(add_net "/0(Rx)")
(add_net "/1(Tx)")
(add_net "/10(**/SS)")
(add_net "/11(**/MISO)")
(add_net "/12(MOSI)")
(add_net "/11(**/MOSI)")
(add_net "/12(MISO)")
(add_net "/13(SCK)")
(add_net /2)
(add_net "/3(**)")
@ -218,9 +218,9 @@
(pad 13 thru_hole oval (at 30.48 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 13 "/10(**/SS)"))
(pad 14 thru_hole oval (at 33.02 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 14 "/11(**/MISO)"))
(net 31 "/11(**/MOSI)"))
(pad 15 thru_hole oval (at 35.56 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 15 "/12(MOSI)"))
(net 32 "/12(MISO)"))
(model ${KIPRJMOD}/Socket_Arduino_Nano.3dshapes/Socket_header_Arduino_1x15.wrl
(at (xyz 0.7 0 0))
(scale (xyz 1 1 1))
@ -251,35 +251,35 @@
(fp_line (start 36.83 1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole oval (at 0 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 16 /Vin))
(net 14 /Vin))
(pad 2 thru_hole oval (at 2.54 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 4 GND))
(pad 3 thru_hole oval (at 5.08 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 3 /Reset))
(pad 4 thru_hole oval (at 7.62 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 17 +5V))
(net 15 +5V))
(pad 5 thru_hole oval (at 10.16 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 18 /A7))
(net 16 /A7))
(pad 6 thru_hole oval (at 12.7 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 19 /A6))
(net 17 /A6))
(pad 7 thru_hole oval (at 15.24 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 20 /A5))
(net 18 /A5))
(pad 8 thru_hole oval (at 17.78 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 21 /A4))
(net 19 /A4))
(pad 9 thru_hole oval (at 20.32 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 22 /A3))
(net 20 /A3))
(pad 10 thru_hole oval (at 22.86 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 23 /A2))
(net 21 /A2))
(pad 11 thru_hole oval (at 25.4 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 24 /A1))
(net 22 /A1))
(pad 12 thru_hole oval (at 27.94 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 25 /A0))
(net 23 /A0))
(pad 13 thru_hole oval (at 30.48 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 26 /AREF))
(net 24 /AREF))
(pad 14 thru_hole oval (at 33.02 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 32 +3V3))
(net 30 +3V3))
(pad 15 thru_hole oval (at 35.56 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 27 "/13(SCK)"))
(net 25 "/13(SCK)"))
(model ${KIPRJMOD}/Socket_Arduino_Nano.3dshapes/Socket_header_Arduino_1x15.wrl
(at (xyz 0.7 0 0))
(scale (xyz 1 1 1))
@ -299,7 +299,7 @@
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 2.54 2.54) (drill 1.778) (layers *.Cu *.Mask F.SilkS)
(net 28 "Net-(P3-Pad1)"))
(net 26 "Net-(P3-Pad1)"))
)
(module Socket_Arduino_Nano:1pin_Nano locked (layer F.Cu) (tedit 55211594) (tstamp 55211558)
@ -314,7 +314,7 @@
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 2.54 2.54) (drill 1.778) (layers *.Cu *.Mask F.SilkS)
(net 29 "Net-(P4-Pad1)"))
(net 27 "Net-(P4-Pad1)"))
)
(module Socket_Arduino_Nano:1pin_Nano locked (layer F.Cu) (tedit 552115A5) (tstamp 5521155D)
@ -329,7 +329,7 @@
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 2.54 2.54) (drill 1.778) (layers *.Cu *.Mask F.SilkS)
(net 30 "Net-(P5-Pad1)"))
(net 28 "Net-(P5-Pad1)"))
)
(module Socket_Arduino_Nano:1pin_Nano locked (layer F.Cu) (tedit 552115BD) (tstamp 55211562)
@ -344,7 +344,7 @@
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 2.54 2.54) (drill 1.778) (layers *.Cu *.Mask F.SilkS)
(net 31 "Net-(P6-Pad1)"))
(net 29 "Net-(P6-Pad1)"))
)
(gr_text 1 (at 141.732 71.247) (layer F.SilkS)