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o Fix line-endings to be canonical.

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This commit is contained in:
Henner Zeller 2015-06-26 06:43:07 -07:00
parent 640417d926
commit 4c18072249
2 changed files with 37 additions and 37 deletions
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46
library/Lattice.dcm
View file

@ -1,23 +1,23 @@
EESchema-DOCLIB Version 2.0
#
$CMP GAL16V8
D Programmable Logic Array, DIP-20/SOIC-20/PLCC-20
K GAL PLD 16V8
$ENDCMP
#
$CMP PAL16L8
D Programmable Logic Array, DIP-20
K PAL PLD 16L8
$ENDCMP
#
$CMP PAL20L8
D Programmable Logic Array, DIP-24
K PAL PLD 20L8
$ENDCMP
#
$CMP PAL20RS10
D Programmable Logic Array, DIP-24 (Narrow)
K PAL PLD 20RS10
$ENDCMP
#
#End Doc Library
EESchema-DOCLIB Version 2.0
#
$CMP GAL16V8
D Programmable Logic Array, DIP-20/SOIC-20/PLCC-20
K GAL PLD 16V8
$ENDCMP
#
$CMP PAL16L8
D Programmable Logic Array, DIP-20
K PAL PLD 16L8
$ENDCMP
#
$CMP PAL20L8
D Programmable Logic Array, DIP-24
K PAL PLD 20L8
$ENDCMP
#
$CMP PAL20RS10
D Programmable Logic Array, DIP-24 (Narrow)
K PAL PLD 20RS10
$ENDCMP
#
#End Doc Library

28
library/Zilog.dcm
View file

@ -1,14 +1,14 @@
EESchema-DOCLIB Version 2.0
#
$CMP Z80CPU
D 8-bit General Purpose Microprocessor, DIP-40
K Z80 CPU uP
F www.zilog.com/manage_directlink.php?filepath=docs/z80/um0080
$ENDCMP
#
$CMP Z8530
D SCC Serial Communication Controller, DIP-40
K SCC Serial Communication
$ENDCMP
#
#End Doc Library
EESchema-DOCLIB Version 2.0
#
$CMP Z80CPU
D 8-bit General Purpose Microprocessor, DIP-40
K Z80 CPU uP
F www.zilog.com/manage_directlink.php?filepath=docs/z80/um0080
$ENDCMP
#
$CMP Z8530
D SCC Serial Communication Controller, DIP-40
K SCC Serial Communication
$ENDCMP
#
#End Doc Library