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Add library symbol for SiFive FE310-G000 microcontroller.

Browse source 
https://static.dev.sifive.com/SiFive-FE310-G000-datasheet-v1p5.pdf
This commit is contained in:
Patrick Pelletier 2017-09-29 11:26:26 -07:00
parent 719377493a
commit 46f1cb3996
2 changed files with 70 additions and 0 deletions
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6
library/microcontrollers.dcm
View file

@ -6,6 +6,12 @@ K 8051 CORE MCU ADC DAC
F http://www.analog.com/static/imported-files/data_sheets/ADUC816.pdf
$ENDCMP
#
$CMP FE310-G000
D 32-bit RISC-V microcontroller
K microcontroller RISC-V SiFive
F https://static.dev.sifive.com/SiFive-FE310-G000-datasheet-v1p5.pdf
$ENDCMP
#
$CMP P89LPC832A1FA
D P89LPC932A1FA, 8kB Flash, 256 SRAM, 8bit MCS51 2-cycle Core Microcontroller, PLCC-28
K Philips 8051 Turbo Core

64
library/microcontrollers.lib
View file

@ -68,6 +68,70 @@ X (AD4)P0.4 49 1100 1100 150 L 50 50 1 1 T
ENDDRAW
ENDDEF
#
# FE310-G000
#
DEF FE310-G000 U 0 40 Y Y 1 F N
F0 "U" -1050 1250 50 H V L CNN
F1 "FE310-G000" -1050 1350 50 H V L CNN
F2 "Housings_DFN_QFN:QFN-48-1EP_6x6mm_Pitch0.4mm_ThermalVias" -1050 1450 50 H I L CNN
F3 "" -1050 1250 50 H I C CNN
$FPLIST
QFN*
$ENDFPLIST
DRAW
S -1050 1150 1050 -1150 0 1 10 f
X QSPI_DQ_3 1 -1200 -100 150 R 50 50 1 1 B
X QSPI_DQ_2 2 -1200 0 150 R 50 50 1 1 B
X QSPI_DQ_1 3 -1200 100 150 R 50 50 1 1 B
X QSPI_DQ_0 4 -1200 200 150 R 50 50 1 1 B
X ~QSPI_CS 5 -1200 -200 150 R 50 50 1 1 O
X VDD 6 100 1300 150 D 50 50 1 1 W
X PLL_AVDD 7 600 1300 150 D 50 50 1 1 W
X PLL_AVSS 8 300 -1300 150 U 50 50 1 1 W
X XTAL_XI 9 -1200 1000 150 R 50 50 1 1 I
X XTAL_XO 10 -1200 900 150 R 50 50 1 1 O
X AON_PSD_LFALTCLK 20 -1200 -900 150 R 50 50 1 1 I
X VDD 30 200 1300 150 D 50 50 1 1 W
X GPIO_18 40 1200 -400 150 L 50 50 1 1 B
X IVDD 11 -400 1300 150 D 50 50 1 1 W
X AON_PSD_LFCLKSEL 21 -1200 -1000 150 R 50 50 1 1 I
X GPIO_5 31 1200 400 150 L 50 50 1 1 B
X GPIO_19 41 1200 -500 150 L 50 50 1 1 B
X OTP_AIVDD 12 -100 1300 150 D 50 50 1 1 W
X AON_PMU_OUT_0 22 -1200 -500 150 R 50 50 1 1 O
X IVDD 32 -300 1300 150 D 50 50 1 1 W
X GPIO_20 42 1200 -600 150 L 50 50 1 1 B
X JTAG_TCK 13 -1200 700 150 R 50 50 1 1 I
X AON_VDD 23 400 1300 150 D 50 50 1 1 W
X GPIO_9 33 1200 300 150 L 50 50 1 1 B
X GPIO_21 43 1200 -700 150 L 50 50 1 1 B
X JTAG_TDO 14 -1200 600 150 R 50 50 1 1 O
X ~AON_ERST_N 24 -1200 -800 150 R 50 50 1 1 I
X GPIO_10 34 1200 200 150 L 50 50 1 1 B
X GPIO_22 44 1200 -800 150 L 50 50 1 1 B
X JTAG_TMS 15 -1200 500 150 R 50 50 1 1 I
X GPIO_0 25 1200 900 150 L 50 50 1 1 B
X GPIO_11 35 1200 100 150 L 50 50 1 1 B
X GPIO_23 45 1200 -900 150 L 50 50 1 1 B
X JTAG_TDI 16 -1200 400 150 R 50 50 1 1 I
X GPIO_1 26 1200 800 150 L 50 50 1 1 B
X GPIO_12 36 1200 0 150 L 50 50 1 1 B
X VDD 46 300 1300 150 D 50 50 1 1 W
X AON_PMU_OUT_1 17 -1200 -600 150 R 50 50 1 1 O
X GPIO_2 27 1200 700 150 L 50 50 1 1 B
X GPIO_13 37 1200 -100 150 L 50 50 1 1 B
X IVDD 47 -200 1300 150 D 50 50 1 1 W
X ~AON_PMU_DWAKEUP_N 18 -1200 -700 150 R 50 50 1 1 I
X GPIO_3 28 1200 600 150 L 50 50 1 1 B
X GPIO_16 38 1200 -200 150 L 50 50 1 1 B
X QSPI_SCK 48 -1200 -300 150 R 50 50 1 1 O
X AON_IVDD 19 500 1300 150 D 50 50 1 1 W
X GPIO_4 29 1200 500 150 L 50 50 1 1 B
X GPIO_17 39 1200 -300 150 L 50 50 1 1 B
X GND 49 100 -1300 150 U 50 50 1 1 W
ENDDRAW
ENDDEF
#
# P89LPC832A1FA
#
DEF P89LPC832A1FA U 0 40 Y Y 1 F N