diff --git a/library/allegro.lib b/library/allegro.lib
index e3d403ef..41f56961 100644
--- a/library/allegro.lib
+++ b/library/allegro.lib
@@ -4,9 +4,9 @@ EESchema-LIBRARY Version 2.3
 # ACS706ELC-05C
 #
 DEF ACS706ELC-05C U 0 40 Y Y 1 F N
-F0 "U" -300 450 50 H V L CNN
-F1 "ACS706ELC-05C" -300 350 50 H V L CNN
-F2 "Housings_SOIC:SOIC-8_3.9x4.9mm_Pitch1.27mm" -300 -350 50 H I L CIN
+F0 "U" 350 250 50 H V L CNN
+F1 "ACS706ELC-05C" 350 150 50 H V L CNN
+F2 "Housings_SOIC:SOIC-8_3.9x4.9mm_Pitch1.27mm" 350 -100 50 H I L CIN
 F3 "" 0 0 50 H V C CNN
 $FPLIST
  SOIC*
@@ -17,18 +17,18 @@ X IP+ 1 -400 200 100 R 50 50 1 1 P
 X IP+ 2 -400 100 100 R 50 50 1 1 P
 X IP- 3 -400 -100 100 R 50 50 1 1 P
 X IP- 4 -400 -200 100 R 50 50 1 1 P
-X GND 5 400 -200 100 L 50 50 1 1 W
+X GND 5 0 -400 100 U 50 50 1 1 W
 X VIout 7 400 0 100 L 50 50 1 1 O
-X VCC 8 400 200 100 L 50 50 1 1 W
+X VCC 8 0 400 100 D 50 50 1 1 W
 ENDDRAW
 ENDDEF
 #
 # ACS711xLCTR-12AB
 #
 DEF ACS711xLCTR-12AB U 0 40 Y Y 1 F N
-F0 "U" -300 550 50 H V L CNN
-F1 "ACS711xLCTR-12AB" -300 450 50 H V L CNN
-F2 "Housings_SOIC:SOIC-8_3.9x4.9mm_Pitch1.27mm" -300 -450 50 H I L CIN
+F0 "U" 350 350 50 H V L CNN
+F1 "ACS711xLCTR-12AB" 350 250 50 H V L CNN
+F2 "Housings_SOIC:SOIC-8_3.9x4.9mm_Pitch1.27mm" 350 -50 50 H I L CIN
 F3 "" 0 0 50 H V C CNN
 ALIAS ACS711xLCTR-25AB
 $FPLIST
@@ -40,10 +40,10 @@ X IP+ 1 -400 300 100 R 50 50 1 1 P
 X IP+ 2 -400 200 100 R 50 50 1 1 P
 X IP- 3 -400 -200 100 R 50 50 1 1 P
 X IP- 4 -400 -300 100 R 50 50 1 1 P
-X GND 5 400 -300 100 L 50 50 1 1 W
+X GND 5 0 -500 100 U 50 50 1 1 W
 X ~FAULT 6 400 -200 100 L 50 50 1 1 O
 X VIout 7 400 100 100 L 50 50 1 1 O
-X VCC 8 400 300 100 L 50 50 1 1 W
+X VCC 8 0 500 100 D 50 50 1 1 W
 ENDDRAW
 ENDDEF
 #