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Fix Pin VSS grid, fix footprint format

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slartibartfas81 2017-04-25 17:07:00 +02:00 committed by GitHub
parent ee6e681a12
commit 20973970d8
1 changed files with 3 additions and 3 deletions
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6
library/stm8.lib
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@ -6,20 +6,20 @@ EESchema-LIBRARY Version 2.3
DEF STM8AF6223 U 0 40 Y Y 1 F N
F0 "U" -800 900 50 H V L CNN
F1 "STM8AF6223" -750 800 50 H V L CNN
F2 "TSSOP20" -650 -900 50 H I L CIN
F2 "Housings_SSOP:TSSOP-20_4.4x6.5mm_Pitch0.65mm" -650 -900 50 H I L CIN
F3 "" -300 -400 50 H I C CNN
$FPLIST
TSSOP20*
$ENDFPLIST
DRAW
S -750 750 750 -800 0 1 10 f
S -750 750 750 -850 0 1 10 f
X PD4 1 -900 0 150 R 50 50 1 1 B
X PD5/UART_TX 2 -900 -100 150 R 50 50 1 1 B
X PD6/UART_RX 3 -900 -200 150 R 50 50 1 1 B
X NRST 4 -900 600 150 R 50 50 1 1 I
X OSCI/PA1 5 900 600 150 L 50 50 1 1 B
X OSCOUT/PA2 6 900 500 150 L 50 50 1 1 B
X VSS 7 0 -950 150 U 50 50 1 1 W
X VSS 7 0 -1000 150 U 50 50 1 1 W
X Vcap 8 -900 -600 150 R 50 50 1 1 I
X VDD 9 0 900 150 D 50 50 1 1 W
X PB5/I2C_SDA 10 900 -100 150 L 50 50 1 1 B